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US 2019/0295960 A1Published application
Dummy Fin Etch to Form Recesses in Substrate
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWan-Chun Kuan, Chih-Teng Liao, Yi-Wei Chiu, Tzu-Chan Weng
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Abstract
An integrated circuit structure includes a semiconductor substrate having a plurality of semiconductor strips, a first recess being formed by two adjacent semiconductor strips among the plurality of semiconductor strips, a second recess being formed within the first recess, and an isolation region being provided in the first recess and the second recess. The second recess has a lower depth than the first recess.
Claims20
An integrated circuit structure comprising:
- a semiconductor substrate comprising a semiconductor strip, wherein the semiconductor strip comprises:
- a base;
- and
- a plurality of semiconductor fins directly over and connected to the base;
- an isolation region in the semiconductor substrate, the isolation region comprising:
- an upper portion at a same level as the base;
- and
- a lower portion extending lower than the base.
5 more elements
An integrated circuit structure comprising:
- a semiconductor substrate;
- a semiconductor strip comprised in the semiconductor substrate, wherein the semiconductor strip is a crown-shaped semiconductor strip comprising:
- a base;
- and
- a plurality of semiconductor fins directly over and joined to the base;
- an isolation region extending into the semiconductor substrate, wherein the isolation region comprises a bottom surface, and the bottom surface comprises:
- at least one first portion;
- and
- a plurality of second portions lower than the at least one first portion, wherein the plurality of second portions are separated from each other by the at least one first portion.
6 more elements
An integrated circuit structure comprising:
- a semiconductor substrate comprising a bulk portion;
- a crown-shaped semiconductor strip comprising:
- a base over a top surface of, and joined to, the bulk portion of the semiconductor substrate;
- and
- a plurality of semiconductor fins overlapping and joined to the base;
- a single-fin semiconductor strip comprising a lower portion level with the base, and an upper portion level with the plurality of semiconductor fins;
- and
- an isolation region, wherein the isolation region comprises:
- a first portion higher than the top surface of the bulk portion, wherein the first portion comprises a first sidewall contacting a second sidewall of the lower portion of the single-fin semiconductor strip;
- and
- a second portion lower than the top surface of the bulk portion.
8 more elements
Dependencies are inferred from the claim text.