Semiconductor memory device

A semiconductor memory device comprising:

• a first interconnect layer provided above a semiconductor substrate;
• a first insulating layer and a second interconnect layer stacked in order on the first interconnect layer;
• and
• a memory pillar penetrating the first insulating layer and the second interconnect layer so that a bottom surface of the memory pillar reaches an inner portion of the first interconnect layer, and including a second insulating layer, a charge storage layer, and a third insulating layer, which are stacked on a part of a side surface including an area in contact with the second interconnect layer and on a bottom surface of the memory pillar, and a first silicide layer in contact with the first interconnect layer, a semiconductor layer, and a second silicide layer, which are stacked in order along a first direction perpendicular to the semiconductor substrate,
• wherein, in the first direction, a height position of a bottom surface of the first silicide layer is lower than a top surface of the first interconnect layer, and a height position of a top surface of the first silicide layer is higher than a bottom surface of the second interconnect layer.