High density antifuse co-integrated with vertical fet

A semiconductor device comprising a vertical transistor co-integrated with an anti-fuse, comprising:

• a highly doped source of a first conductivity type overlying a substrate;
• a counter-doped layer of a second conductivity type arranged between the highly doped source and the substrate;
• a first channel region extending over the highly doped source and comprising an epitaxial growth, the first channel region located at a first location on the substrate and having a first width;
• a drain comprising an epitaxial growth arranged on the channel region, the channel region extending from the highly doped source to the drain;
• and
• a highly doped fuse region extending over the highly doped source and comprising an epitaxial growth, the highly doped fuse region located at a second location on the substrate and having a second width that is larger than the first width.