Semiconductor package of using insulating frame
AssigneeNepes Co., Ltd.
InventorsYongtae KWON, Junkyu LEE, Jaecheon LEE, Mina YOON
Life of this patent
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Abstract
A semiconductor package using an insulating frame of various is disclosed. The insulating frame has a through hole therein, and the semiconductor chip is mounted in the through hole. Further, a via hole is provided in the periphery of the through hole, and a via contact filling the via hole is provided. Whereby the pad of the semiconductor chip is electrically connected to the via contact through the distribution layer. Further, an adhesive buffer layer for increasing the adhesive force is introduced into the upper portion of the insulating frame.
Claims20
A semiconductor package comprising:
- an insulating frame having a through hole, a first surface and a second surface facing the first surface;
- a semiconductor chip disposed in the through hole and having an active surface on which a pad is formed;
- a molding layer covering a back surface and side surface of the semiconductor chip by filling the through hole, and being coplanar with the first surface of the insulating frame;
- a redistribution layer electrically connected to the pad of the semiconductor chip, and formed on the active surface of the semiconductor chip and on the first surface of the insulating frame;
- and
- an external connection terminal electrically connected to the pad of the semiconductor chip, and formed on the redistribution layer,
- wherein the first surface and the second surface of the insulating frame have different widths from each other, or an inner circumferential surface of the insulating frame has an inclined surface.
A semiconductor package comprising:
- an insulating frame having a first through hole formed from first surface, and a second through hole formed from a second surface opposing to the first surface and having width narrower than width of the first through hole a semiconductor chip disposed in the first through hole;
- a molding layer filling space between the semiconductor chip and the first through hole, and the second through hole, so that the molding layer covers a back surface and side surface of the semiconductor chip and is coplanar with the first surface of the insulating frame;
- a conductive layer formed on the molding layer and having a higher conductivity than the molding layer;
- an upper redistribution layer formed on an active surface of the semiconductor chip and the first surface of the insulating frame, and electrically connected to a pad on the active surface of the semiconductor chip;
- and
- a via contact passing through the insulating frame, filling via hole formed in peripheral region of the first through hole, and electrically connected to the upper redistribution layer,
- wherein the molding layer and the conductive layer are formed in the though hole.
A semiconductor package comprising:
- an adhesive buffer layer formed on the insulating frame;
- a polymer bonding layer formed on the adhesive buffer layer and provided as an insulating polymer film;
- and
- a wiring layer formed on the polymer bonding layer,
- wherein the adhesive buffer layer is metal film or nanoparticle film, and the nanoparticle film has TiO2 or SiO2.
Dependencies are inferred from the claim text.