Arrays Of Memory Cells Individually Comprising A Capacitor And A Transistor And Methods Of Forming Such Arrays
AssigneeMicron Technology, Inc.
InventorDurai Vishak Nirmal Ramaswamy
Life of this patent
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Abstract
An array of memory cells individually comprising a capacitor and a transistor comprises, in a first level, alternating columns of digitlines and conductive shield lines. In a second level above the first level there are rows of transistor wordlines. In a third level above the second level there are rows and columns of capacitors. In a fourth level above the third level there are rows of transistor wordlines. In a fifth level above the fourth level there are alternating columns of digitlines and conductive shield lines. Other embodiments and aspects are disclosed, including method.
Claims24
1-29. (canceled)
An array of memory cells individually comprising a capacitor and a transistor, comprising:
- a first array comprising:
- in a first level, alternating columns of digitlines and conductive shield lines;
- in a second level above the first level, rows of transistor wordlines;
- in a third level above the second level, rows and columns of capacitors;
- in a fourth level above the third level, rows of transistor wordlines;
- and
- in a fifth level above the fourth level, alternating columns of digitlines and conductive shield lines;
- and
- another of said first array directly above said first array.
An array of memory cells individually comprising a capacitor and a transistor, comprising:
- a first array comprising:
- in a first level, alternating columns of digitlines and conductive shield lines;
- in a second level above the first level, rows of transistor wordlines;
- in a third level above the second level, rows and columns of capacitors;
- in a fourth level above the third level, rows of transistor wordlines;
- in a fifth level above the fourth level, alternating columns of digitlines and conductive shield lines;
- and
- the memory cells individually having a total of only one transistor and a total of only one capacitor;
- and
- another of said first array directly above said first array, the first level of the another of said first array being directly above the fifth level of the first array.
An array of memory cells individually comprising a capacitor and a transistor, comprising:
- a first array comprising:
- in a first level, alternating columns of digitlines and conductive shield lines;
- in a second level above the first level, rows of transistor wordlines;
- in a third level above the second level, rows and columns of capacitors;
- in a fourth level above the third level, rows of transistor wordlines;
- in a fifth level above the fourth level, alternating columns of digitlines and conductive shield lines;
- and
- the memory cells individually having a total of only one transistor and a total of only one capacitor;
- and
- another of said first array directly above said first array, the fifth level of the first array being the first level of the another of said first array such that the alternating columns of digitlines and conductive shield lines therein are shared by the first array and the another of said first array.
An array of memory cells individually comprising a capacitor and a transistor, comprising:
- a first array comprising:
- in a first level, alternating columns of digitlines and conductive shield lines, the digitlines being elongated in a column direction;
- in a second level above the first level, rows of transistor wordlines, the rows being elongated in row direction;
- in a third level above the second level, rows and columns of capacitors;
- in a fourth level above the third level, rows of transistor wordlines;
- in a fifth level above the fourth level, alternating columns of digitlines and conductive shield lines;
- the memory cells individually having a total of only one transistor and a total of only one capacitor, the transistors individually comprising a channel region, the transistor wordlines being laterally over opposing sides of individual of the channel regions in the row direction;
- and
- another of said first array directly above said first array.
An array of memory cells individually comprising a capacitor and a transistor, comprising:
- a first array comprising:
- in a first level, alternating columns of digitlines and conductive shield lines, the digitlines being elongated in a column direction;
- in a second level above the first level, rows of transistor wordlines, the rows being elongated in row direction;
- in a third level above the second level, rows and columns of capacitors;
- in a fourth level above the third level, rows of transistor wordlines;
- in a fifth level above the fourth level, alternating columns of digitlines and conductive shield lines;
- the memory cells individually having a total of only one transistor and a total of only one capacitor, the transistors individually comprising a channel region, the transistor wordlines being laterally over opposing sides of individual of the channel regions in the column direction;
- and
- another of said first array directly above said first array.
An array of memory cells individually comprising a capacitor and a transistor, comprising:
- a first array comprising:
- in a first level, alternating columns of digitlines and conductive shield lines, the digitlines being elongated in a column direction;
- in a second level above the first level, rows of transistor wordlines, the rows being elongated in row direction;
- in a third level above the second level, rows and columns of capacitors;
- in a fourth level above the third level, rows of transistor wordlines;
- in a fifth level above the fourth level, alternating columns of digitlines and conductive shield lines;
- the memory cells individually having a total of only one transistor and a total of only one capacitor, the transistors individually comprising a channel region, the transistor wordlines being laterally surrounding all sides of individual of the channel regions;
- and
- another of said first array directly above said first array.
Dependencies are inferred from the claim text.