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US 2019/0295940 A1Published application
Interconnect Structure in Semiconductor Devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon Jhy Liaw
Life of this patent
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Abstract
A semiconductor device includes transistors over a substrate, and first, second, and third metallization layers over the transistors. The first, second, and third metallization layer includes first, second, and third metal features, respectively. The second metal features are oriented lengthwise substantially perpendicular to the first metal features, and the third metal features are oriented lengthwise substantially parallel to the first metal features. The first, second, and third metal features have a first, second, and third thickness, respectively, along a first direction perpendicular to a top surface of the substrate. The second thickness is smaller than both the first and the third thicknesses.
Claims20
A semiconductor device, comprising:
- transistors formed over a substrate;
- a first metallization layer over the transistors, the first metallization layer including first metal features disposed in a first dielectric layer, the first metal features having a first thickness along a first direction perpendicular to a top surface of the substrate;
- a second metallization layer over the first metallization layer, the second metallization layer including second metal features disposed in a second dielectric layer, the second metal features having a second thickness along the first direction;
- and
- a third metallization layer over the second metallization layer, the third metallization layer including third metal features disposed in a third dielectric layer, the third metal features having a third thickness along the first direction, wherein the second thickness is smaller than both the first and the third thicknesses, the second metal features are oriented lengthwise substantially perpendicular to the first metal features, and the third metal features are oriented lengthwise substantially parallel to the first metal features.
2 more elements
A semiconductor device, comprising:
- FinFET transistors over a substrate, the FinFET transistors being arranged into abutting standard cells, each standard cell including a p-type FinFET transistor and an n-type FinFET transistor, gate stacks of the FinFET transistors being oriented lengthwise along a first direction;
- a first metallization layer over the FinFET transistors, the first metallization layer including first metal features disposed in a first dielectric layer, the first metal features being oriented lengthwise along a second direction substantially perpendicular to the first direction, the first metal features having a first thickness along a third direction perpendicular to a top surface of the substrate;
- a second metallization layer over the first metallization layer, the second metallization layer including second metal features disposed in a second dielectric layer, the second metal features being oriented lengthwise substantially parallel to the first direction, the second metal features having a second thickness along the third direction;
- and
- a third metallization layer over the second metallization layer, the third metallization layer including third metal features disposed in a third dielectric layer, the third metal features being oriented lengthwise substantially parallel to the second direction, the third metal features having a third thickness along the first direction, wherein the second thickness is smaller than both the first and the third thicknesses.
2 more elements
A semiconductor device, comprising:
- FinFET transistors over a substrate, the FinFET transistors including fins oriented lengthwise along a first direction and gate stacks oriented lengthwise along a second direction substantially perpendicular to the first direction, the FinFET transistors being arranged into abutting standard cells, each standard cell having a substantially rectangular boundary;
- a first metallization layer over the FinFET transistors, the first metallization layer including first metal features disposed in a first dielectric layer, the first metal features being oriented lengthwise substantially parallel to the first direction, the first metal features including conductors for routing power and ground lines of the semiconductor device, the first metal features having a first thickness along a third direction perpendicular to the first and the second directions;
- and
- a second metallization layer over the first metallization layer, the second metallization layer including second metal features disposed in a second dielectric layer, the second metal features being oriented lengthwise substantially parallel to the second direction, the second metal features including conductors for routing signal lines within the boundary of each standard cell, the second metal features having a second thickness along the third direction, wherein the second thickness is smaller than the first thicknesses by at least 10%.
1 more element
Dependencies are inferred from the claim text.