Discrete electronic device embedded in chip module

A multilayer substrate panel for manufacturing a plurality of chip modules with a plurality of discrete electronic devices embedded therein, the plurality of discrete electronic devices peripherally distributed around each one of the chip modules, the multilayer substrate panel comprising:

• a plurality of chip modules, each chip module comprising:
• a part of the multilayer substrate panel with a horizontal top surface, a horizontal bottom surface and one or more vertical side surfaces extending peripherally between the top surface and the bottom surface;
• one or more of the plurality of chip modules being configured to receive one or more of the plurality of discrete electronic devices to be mounted onto the horizontal top surface, the chip module further being configured to be mounted on a printed circuit board;
• a plurality of horizontal electrically conductive layers with adjacent electrically conductive layers of the plurality of horizontal electrically conductive layers being separated from each other by a horizontal electrically non-conductive layer;
• a plurality of predefined electrically non-conductive portions for embedding a second device of the plurality of discrete electronic devices, each of the plurality of predefined portions extending vertically through a subset plurality of horizontal electrically conductive layers;
• for each predefined portion a first layer of the plurality of horizontal electrically conductive layers comprises an electrically non-conductive clearance along a first part of a circumferential boundary of the respective predefined portion and an electrically conductive structure reaching to a second part of the circumferential boundary of the respective predefined portion;
• for each predefined portion a second layer of the electrically conductive layers comprises an electrically non-conductive clearance along the second part of the circumferential boundary of the respective predefined portion and an electrically conductive structure reaching to the first part of the circumferential boundary of the respective predefined portion;
• and
• a size of each predefined portion being configured to be provided with a recess for receiving a discrete electronic device comprising a first and a second electrical contact spaced apart from each other such that a first electrically conductive connection is established between the first electrical contact and a electrically conductive structure of the first of the plurality of horizontal electrically conductive layers, and such that a second electrically conductive connection is established between the second electrical contact and the second layer of the plurality of electrically conductive structures of the second electrically conductive layer.

A multilayer substrate panel for manufacturing a plurality of chip modules with a plurality of discrete electronic devices embedded therein, the plurality of discrete electronic devices peripherally distributed around each one of the chip modules, the multilayer substrate panel comprising:

• a plurality of chip modules, each chip module comprising:
• a part of the multilayer substrate panel with a horizontal top surface, a horizontal bottom surface and one or more vertical side surfaces extending peripherally between the top surface and the bottom surface;
• one or more of the plurality of chip modules being configured to receive one or more of the plurality of discrete electronic devices to be mounted onto the horizontal top surface, the chip module further being configured to be mounted on a printed circuit board;
• a plurality of horizontal electrically conductive layers with adjacent electrically conductive layers of the plurality of horizontal electrically conductive layers being separated from each other by a horizontal electrically non-conductive layer;
• and
• a plurality of predefined electrically non-conductive portions for embedding a second device of the plurality of discrete electronic devices, each of the plurality of predefined portions extending vertically through a subset plurality of horizontal electrically conductive layers.