Package substrates with magnetic build-up layers
AssigneeIntel Corporation
InventorsZHIGUO QIAN, KALADHAR RADHAKRISHNAN, KEMAL AYGUN
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Abstract
The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.
Claims25
A semiconductor interconnect, comprising:
- a substrate having a first surface and a transversely opposed second surface;
- at least one magnetic build-up layer disposed proximate the first surface of the substrate;
- a plurality of bump pads disposed across at least a portion of the second surface of the substrate;
- a plurality of conductive ball pads having a first capacitance at a first frequency disposed across at least a portion of the surface of the substrate, each of at least some of the plurality of conductive ball pads disposed proximate the at least one magnetic build-up layer;
- and
- a plurality of conductive vias, each of the plurality of vias conductively coupling at least one of the plurality of bump pads to a respective one of the plurality of conductive ball pads, the at least one magnetic build-up layer disposed about at least a portion of an external perimeter of each of at least some of the plurality of conductive vias.
A semiconductor interconnect fabrication method, comprising:
- disposing at least one magnetic build-up layer proximate at least a portion of a first surface of a substrate;
- forming a plurality of vias in the substrate, each of at least some of the plurality of vias passing through the at least one magnetic build-up layer such that the at least one magnetic build-up layer is disposed about at least a portion of an external perimeter of the respective via;
- forming a plurality of bump pads across at least a portion of a second surface of the substrate, the second surface transversely opposed across a thickness of the substrate to the first surface,
- conductively coupling each of at least a portion of the plurality of bump pads to a respective one of the plurality of vias;
- and
- forming a plurality of conductive ball pads across at least a portion of the first surface of the substrate, each of at least a portion of the plurality of conductive ball pads disposed proximate the at least one magnetic build-up layer, each of the conductive ball pads having a first capacitance at a first frequency;
- and
- conductively coupling each of at least a portion of the plurality of conductive ball pads to a respective one of the plurality of vias.
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An electronic device, comprising:
- a system substrate;
- at least one semiconductor package that includes:
- a semiconductor die;
- and
- a semiconductor interconnect, comprising:
- a substrate having a first surface and a transversely opposed second surface;
- at least one magnetic build-up layer disposed proximate the first surface of the substrate;
- a plurality of bump pads to receive the semiconductor die disposed across at least a portion of the second surface of the substrate;
- a plurality of conductive ball pads having a first capacitance at a first frequency disposed across at least a portion of the surface of the substrate, each of at least some of the plurality of conductive ball pads disposed proximate the at least one magnetic build-up layer;
- and
- a plurality of conductive vias, each of the plurality of vias conductively coupling at least one of the plurality of bump pads to a respective one of the plurality of conductive ball pads, the at least one magnetic build-up layer disposed about at least a portion of an external perimeter of each of at least some of the plurality of conductive vias.
Dependencies are inferred from the claim text.