US 2019/0295899 A1 · Source and Drain Isolation for CMOS Nanosheet with One Block Mask

Abstract

Techniques for source/drain isolation in nanosheet devices are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of sacrificial/active channel nanosheets as a stack on a substrate; forming gates on the stack; forming spacers alongside opposite sidewalls of the gates; patterning the stack, in between the spacers, into individual PFET/NFET stacks and pockets in the substrate; laterally recessing the sacrificial nanosheets in the PFET/NFET stacks to expose tips of the active channel nanosheets in the PFET/NFET stacks; forming inner spacers alongside the PFET/NFET stacks covering the tips of the active channel nanosheets; forming a protective layer lining the pockets; and selectively etching back the inner spacers to expose tips of the active channel nanosheets and epitaxially growing source and drains from the exposed tips of the active channel nanosheets sequentially in the PFET/NFET stacks. A nanosheet device is also provided.

Claims20

Dependent claims

A nanosheet device, comprising:

individual PFET and NFET stacks on a substrate, wherein the PFET and NFET stacks each comprises active channel nanosheets;
pockets in the substrate between the PFET and NFET stacks;
an oxide protective layer lining the pockets in the substrate;
epitaxial source and drains on opposite sides of the PFET and NFET stacks;
gates surrounding at least a portion of each of the active channel nanosheets;
and
inner spacers offsetting the gates from the epitaxial source and drains.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/440,095Filed 13 Jun 2019

Priority

10 Jan 2018

Published

26 Sep 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification28 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
B82Y 10/00
Nanotechnology for information processing, storage or transmission
H10D 30/014
Manufacture or treatment: of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron…
H10D 30/0195
Of FETs having stacked nanowire, nanosheet or nanoribbon channels: forming inner spacers between adjacent channels, e.g. changing their shapes or…

Source and Drain Isolation for CMOS Nanosheet with One Block Mask

Life of this patent

Source and Drain Isolation for CMOS Nanosheet with One Block Mask

Life of this patent

Abstract

Claims20