Vertical fet devices with multiple channel lengths
AssigneeInternational Business Machines Corporation
InventorsHari V. Mallela, Reinaldo A. Vega, Rajasekhar Venigalla
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Abstract
A semiconductor device comprises a first source/drain region arranged on a semiconductor substrate, a second source/drain region arranged on the semiconductor substrate, a bottom spacer arranged on the first source/drain region, and a bottom spacer arranged on the second source/drain region. A first gate stack having a first length is arranged on the first source/drain region. A second gate stack having a second length is arranged on the second source/drain region, the first length is shorter than the second length. A top spacer is arranged on the first gate stack, and a top spacer is arranged on the second gate stack.
Claims20
A semiconductor device comprising:
- a first channel region on a first source/drain region, the first source/drain region being arranged on a semiconductor substrate;
- a second channel region on a second source/drain region, the second source/drain region being arranged on the semiconductor substrate;
- a bottom spacer arranged on the first source/drain region and on the second source/drain region;
- a first gate stack having a first length arranged on the first source/drain region;
- a second gate stack having a second length arranged on the second source/drain region, the first length is shorter than the second length;
- and
- a top spacer arranged on the first gate stack and the second gate stack.
Dependencies are inferred from the claim text.