Semiconductor package and method of fabricating semiconductor package

A method of forming an interconnection structure, comprising

• providing a substrate having contacts and a dielectric material layer covering the contacts;
• performing a first exposure process with a first energy dose to form first exposure portions in the dielectric material layer;
• performing a second exposure process with a second energy dose to form second exposure portions in the dielectric material layer, wherein the first energy dose is larger than the second energy dose;
• performing a development process dissolving the first exposure portions and the second exposure portions of the dielectric material layer and over-developing the dielectric material layer in the same development process to form via openings larger than the first exposure portions and the trench openings larger than the second exposure portions;
• forming a seed metallic layer over the dielectric material layer and covering the via openings and trench openings;
• and
• forming metal patterns on the seed metallic layer and filled within the via openings and the trench openings.

A semiconductor package, comprising:

• a substrate having contacts;
• a dielectric layer disposed on the substrate;
• a redistribution metallic pattern disposed on the substrate and disposed in the dielectric layer, wherein the redistribution metallic pattern includes at least one via portion disposed on and connected with the contacts and at least one routing line portion connected with the at least one via portion, the at least one routing line portion and the at least one via portion have slant sidewalls;
• and
• a seed metallic pattern sandwiched between the redistribution metallic pattern and the dielectric layer and between the at least one via portion and the contacts.