Semiconductor integrated circuit
AssigneesKabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
InventorKenichi ANZOU
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Abstract
In general, according to one embodiment, there is provided a semiconductor integrated circuit including a memory macro. The memory macro includes a first ECC circuit that generates a code corresponding to input data, a memory core including a data storage portion on which reading and writing of data is performed, and an ECC storage portion on which reading and writing of a code is performed, a second ECC circuit that executes, based on data and code read from the memory core, error detection or correction of the data, and circuits that form a path in which data flows to bypass the memory core in a scan test, and form a path in which data flows through each of the data storage portion and the ECC storage portion in a memory test.
Claims11
A semiconductor integrated circuit comprising a memory macro including:
- a first error correction code (ECC) circuit that generates an error detection and correction code corresponding to input data;
- a memory core including a data storage portion on which reading and writing of data is performed, and an ECC storage portion on which reading and writing of a code is performed;
- a second ECC circuit that performs, based on data and code read from the memory core, error detection or correction of the data;
- and
- circuits that form a path in which data flows to bypass the memory core in a scan test, and form a path in which data flows through each of the data storage portion and the ECC storage portion in a memory test.
Dependencies are inferred from the claim text.