Semiconductor integrated circuit

A semiconductor integrated circuit comprising:

• a memory;
• a built-in self test circuit that writes data into each row of the memory, causes the memory to output data, and outputs an expected value;
• and
• a memory output analysis circuit including
• a first circuit that determines the presence or absence of a first fault based on a comparison between the data outputted from the memory and the expected value,
• a second circuit that determines whether or not the first fault corresponds to a second fault that continues in an address direction when the first fault is detected by the first circuit and outputs a first signal when determining that the first fault corresponds to the second fault, and
• a third circuit that determines whether or not a third fault that does not correspond to the second fault occurs besides the second fault while the first signal is being outputted and outputs a second signal when determining that the third fault occurs,
• wherein the built-in self test circuit determines whether or not to interrupt a test based on at least the first signal and the second signal.