Multi Mode Memory Module with Data Handlers

A memory module operable at an operational speed according to a system clock in a computer system including a system memory controller coupled to a system memory bus having a bit width N, comprising:

• a printed circuit board (PCB) having edge connections that fit into a corresponding slot connector of the computer system whereby the memory module is operatively coupled to the system memory controller of the computer system via the system memory bus;
• memory devices mounted on the PCB and organized in one or more ranks, each rank of the one or more ranks having a width equal to the bit width N of the system memory bus, each of the memory devices having respective address and control ports and respective data ports;
• a plurality of data handlers mounted on the PCB, each respective data handler of the plurality of data handlers being coupled to a respective n-bit-wide portion of the memory devices, where n is smaller than N;
• and
• a control circuit mounted on the PCB and coupled to each of the plurality of data handlers and to the respective address and control ports of each of the memory devices;
• wherein, during a normal memory read or write operation, the control circuit is configurable to receive system address and control signals from the system memory controller via the system memory bus and to output registered memory address and control signals for the normal memory read or write operation, and the each respective data handler is configurable to propagate respective data signals associated with the normal memory read or write operation between the respective n-bit-wide portion of the memory devices and a respective n-bit-wide segment of the system memory bus during the normal memory read or write operation, the respective n-bit-wide portion of the memory devices including at least one respective memory device configurable to receive the registered memory address and control signals via address and control ports of the at least one respective memory device, and to output or receive, via data ports of the at least one respective memory device, the respective data signals associated with the normal memory read or write operation at the operational speed in response to the registered memory address and control signals;
• and
• wherein, while the memory module is not accessed by the system memory controller for any normal memory read or write operation, the control circuit is configurable to output test address and control signals, the each respective data handler is configurable to provide respective test data to be written into the at least one respective memory device by outputting respective test data signals, and the at least one respective memory device is configurable to receive the test address and control signals via the address and control ports of the at least one respective memory device, and to receive, via the data ports of the at least one respective memory device, the respective test data signals at the operational speed in response to the test address and control signals.

A memory module operable in a computer system including a system memory controller coupled to a system memory bus having a bit width N, comprising:

• a printed circuit board (PCB) including a connector that fit into a corresponding slot connector of the computer system whereby the memory module is operatively coupled to the system memory controller of the computer system via the system memory bus;
• memory devices mounted on the PCB and organized in one or more ranks, each rank of the one or more ranks having a width equal to the bit width N of the system memory bus, each of the memory devices having respective address and control ports and respective data ports;
• a data module coupled between the memory devices and the connector, the data module including at least two physically separate integrated circuit packages mounted on different portions of the PCB and coupled to different n-bit-wide portions of the memory devices, where n is smaller than N;
• and
• a control circuit mounted on the PCB and coupled to the connector, the data module, and the respective address and control ports of each of the memory devices;
• wherein, during a normal memory read or write operation, the control circuit is configurable to receive system address and control signals from the system memory controller via the system memory bus and the connector and to output registered memory address and control signals for the normal memory read or write operation, and each respective integrated circuit package of the data module is configurable to propagate respective data signals associated with the normal memory read or write operation between a respective n-bit-wide portion of the memory devices and a respective n-bit-wide segment of the system memory bus during the normal memory read or write operation, the respective n-bit-wide portion of the memory devices including at least one respective memory device configurable to receive the registered memory address and control signals via address and control ports of the at least one respective memory device, and to output or receive, via data ports of the at least one respective memory device, the respective data signals associated with the normal memory read or write operation in response to the registered memory address and control signals;
• and
• wherein, while the memory module is not accessed by the system memory controller for any normal memory read or write operation, the control circuit is configurable to output test address and control signals, the each respective integrated circuit package of the data module is configurable to provide respective test data to be written into the at least one respective memory device by outputting respective test data signals based on information received from the control circuit, and the at least one respective memory device is configurable to receive the test address and control signals via the address and control ports of the at least one respective memory device, and to receive, via the data ports of the at least one respective memory device, the respective test data signals in response to the test address and control signals from the control circuit.