Memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsJin Bae BANG, Joon Suc JANG
Life of this patent
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Abstract
A memory device includes a page buffer unit including a plurality of latches latching each of a plurality of pieces of dummy data of selected memory cells according to a plurality of dummy signals provided by a word line of the selected memory cells, and a control logic comparing a count value of a first count latch among the plurality of latches with a reference count value, determining whether to count a second count latch other than the first count latch according to a result of the comparison, and correcting a level of a read signal provided by the word line of the selected memory cells in a read operation.
Claims21
A memory device comprising:
- a page buffer unit including a plurality of latches, the plurality of latches configured to latch a plurality of pieces of dummy data of selected memory cells based on a plurality of dummy signals provided by a word line of the selected memory cells, the plurality of latches including a first count latch and a second count latch, the first count latch and the second count latch each configured to store a value corresponding to a number of on-cells or off-cells of respective ones of the selected memory cells;
- and
- a control logic configured to,
- determine whether to count the values of the second count latch based on the count value of the first count latch and a reference count value, and
- correct a voltage level of a read signal provided by the word line of the selected memory cells in a read operation based on results of the determination.
A memory device comprising:
- a page buffer unit including a plurality of latches configured to latch a plurality of pieces of dummy data of selected memory cells based on a plurality of dummy signals provided by a word line of the selected memory cells;
- a cell counter connected to the plurality of latches, the cell counter configured to count at least one of the pieces of dummy data;
- a control logic configured to detect a level of deterioration of the selected memory cells to correct a voltage level of a read signal, based on at least one count value output from the cell counter;
- and
- the cell counter is further configured to determine whether to update a piece of the dummy data selected as a count target, based on a level of deterioration of the pieces of dummy data selected as a count target.
A memory device performing a dummy read operation to provide a dummy voltage to a word line of selected memory cells, prior to a read operation providing a read voltage to the word line of the selected memory cells, the memory device comprising:
- a page buffer connected to a memory cell array including a plurality of memory cells, and the page buffer including a plurality of latches;
- a cell counter connected to the plurality of latches, the cell counter configured to count at least one of an on-cell or an off-cell of the memory cells;
- and
- a control logic configured to,
- correct a voltage level of a read signal based on a count value output from the cell counter, in response to the dummy voltage, and
- change a potential of the word line to a desired voltage level of the read signal, after an end of a latch period corresponding to the plurality of latches latching data of the memory cells during the dummy read operation.
(canceled)
Dependencies are inferred from the claim text.