System and method for in-situ programming and read operation adjustments in a non-volatile memory

A system comprising:

• a memory array comprising a plurality of memory cells;
• a plurality of bit lines connected to the plurality of memory cells;
• a detection circuit configured to detect a time duration for a bit line voltage of a bit line of the plurality of bit lines to reach a threshold voltage level during a pre-charge stage of a program-verify operation;
• a timing circuit configured to, during the program operation, determine a bit line settling time period for a verify stage of the program-verify operation corresponding to the detected time duration from a buffer associating a plurality of bit line settling time periods with a plurality of time durations of the pre-charge stage;
• and
• a sense circuit connected to the bit line, the sense circuit configured to, during the verify stage, sense a status of a memory cell coupled to the bit line relative to the bit line settling time period.

A circuit comprising:

• a detection circuit configured to detect a time duration for a word line voltage of a word line to reach a threshold voltage level during a word line charging portion of a read operation for a memory cell coupled to the word line;
• and
• a timing circuit configured to identify a word line settling time period for the word line during a read stage of the read operation based on the time duration detected;
• and
• a sense circuit configured to sense a program state of the memory cell during the read stage relative to the identified word line settling time period.

A method comprising:

• detecting, with a detection circuit, a time at which a bit line voltage increasing from an initial level reaches a threshold level during a pre-charge stage of a program-verify operation;
• outputting, with the detection circuit, a state change signal in response to detecting that the bit line voltage reached the threshold level;
• tracking, with a counter, a number of clock pulses of a clock signal from a beginning of the pre-charge stage to when the state change signal indicates that the bit line voltage reached the threshold level;
• selecting, with verify logic, a bit line settling time period based on the number of clock pulses;
• and
• outputting, with a sense circuit controller, a control signal to a sense circuit in response to expiration of the bit line settling time period.

A method comprising:

• detecting, with a detection circuit, a time at which a word line voltage increasing from an initial level reaches a threshold level during application of a read spike voltage in an initial read stage of a read operation;
• outputting, with the detection circuit, a state change signal in response to detecting that the word line voltage reached the threshold level;
• tracking, with a counter, a number of clock pulses of a clock signal from a beginning of application of the read spike voltage in the initial read stage to when the state change signal indicates that the word line voltage reached the threshold level;
• selecting, with read logic, a word line settling time period based on the number of clock pulses;
• and
• outputting, with a sense circuit controller, a control signal to a sense circuit in response to expiration of the word line settling time period.