Memory devices and apparatus configured to apply positive voltage levels to data lines for memory cells selected for and inhibited from programming

A memory device, comprising:

• a first data line selectively connected to a first end of a first string of series-connected memory cells;
• a second data line selectively connected to a first end of a second string of series-connected memory cells;
• a particular access line coupled to a first memory cell of the first string of series-connected memory cells selected for programming and coupled to a second memory cell of the second string of series-connected memory cells to be inhibited from programming;
• and
• a controller, wherein the controller is configured to cause the memory device to perform a method comprising:
• applying a first voltage level to the first data line while applying the first voltage level to the second data line;
• applying a second voltage level, lower than the first voltage level, to the first data line while continuing to apply the first voltage level to the second data line;
• and
• while applying the second voltage level to the first data line and while applying the first voltage level to the second data line, applying a third voltage level to the particular access line;
• wherein a differential between the third voltage level and the second voltage level is configured to increase a threshold voltage of the first memory cell;
• and
• wherein the second voltage level is a positive voltage level.

An electronic system, comprising:

• a communications interface;
• a memory access device coupled to the communications interface;
• and
• a memory device coupled to the communications interface, the memory device comprising:
• a first data line selectively connected to a first end of a first string of series-connected memory cells;
• a second data line selectively connected to a first end of a second string of series-connected memory cells;
• and
• a controller, wherein the controller is configured to cause the memory device to perform a method comprising:
• applying a positive first voltage level to the first data line while applying a second voltage level, higher than the first voltage level, to the second data line;
• connecting the first data line to the first end of the first string of series-connected memory cells while applying the first voltage level to the first data line and while applying a second voltage level to the second data line;
• isolating the second data line from the first end of the second string of series-connected memory cells while connecting the first data line to the first end of the first string of series-connected memory cells;
• applying a third voltage level to a particular access line coupled to a memory cell of the first string of series-connected memory cells selected for programming while connecting the first data line to the first end of the first string of series-connected memory cells and while isolating the second data line from the first end of the second string of series-connected memory cells;
• wherein the third voltage level applied to the particular access line is configured to increase a threshold voltage of the memory cell selected for programming while connecting the first data line to the first end of the first string of series-connected memory cells;
• and
• wherein the third voltage level applied to the particular access line is configured to inhibit increasing a threshold voltage of a memory cell of the second string of series-connected memory cells coupled to the particular access line while isolating the second data line from the first end of the second string of series-connected memory cells.