Semiconductor device
AssigneeToshiba Memory Corporation
InventorsYasuhiro HIRASHIMA, Masaru KOYANAGI, Mikihiko ITO, Kei SHIRAISHI, Fumiya WATANABE
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Abstract
A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.
Claims20
A semiconductor device comprising:
- an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal,
- wherein a duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.
A semiconductor device comprising:
- an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal, a second comparator configured to output a third output signal based on a comparison result between a third input signal and a first reference signal, and a third comparator configured to output a fourth output signal based on a comparison result between the third input signal and the first reference signal, wherein the third output signal is delayed and combined with the fourth output signal that is delayed to produce a fifth output signal;
- and
- a data latch circuit configured to strobe the fifth output signal using the first output signal or the second output signal and to latch a result of the strobing.
Dependencies are inferred from the claim text.