Memory controller and memory system having the same

A memory controller, comprising:

• a command generator generating first read commands for a plurality of read voltages having different levels respectively, and transferring the first read commands to a memory device so that a first read operation is performed plural times on a plurality of memory cells for each of the read voltages;
• an inverted cell counter determining inverted cells showing different bit values during the first read operation performed plural times for each read voltage on the basis of read result data received from the memory device;
• and
• an optimal read voltage determiner estimating a threshold voltage distribution of the memory cells from a voltage distribution of inverted cells for each of the plurality of read voltages.

A memory system, comprising:

• a memory device performing read operations on a plurality of memory cells;
• and
• a memory controller suitable for:
• generating and transferring two read commands for each of a plurality of read voltages having different levels to the memory device so that two read operations are performed on the plurality of memory cells for each of the plurality of read voltages,
• receiving read data corresponding to results of the two read operations performed on each of the plurality of memory cells from the memory device,
• checking whether inverted cells having inverted read data exist among the plurality of memory cells by comparing the read data, and
• counting checked inverted cells for each of the read voltages.

An operating method of a memory system, the method comprising:

• performing plural times a preliminary read operation on memory cells for each of different read voltages;
• selecting one or more optimal read voltages among the read voltages based on a number of inverted read values detected for each of the read voltages;
• and
• performing a primary read operation on the memory cells with the optimal read voltages.