Sram memory
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMichael Clinton, Bryan David Sheffield, Marty Tsai, Rajinder Singh
Life of this patent
Estimating the term…
Abstract
A memory device includes an array of memory cells that has a first sub array and a second sub array. A plurality of bit lines are connected to the memory cells, and an IO block is situated between the first sub array and the second sub array. The bit lines extend from the first and second memory sub arrays of the memory device directly to the IO block. The IO block further includes data input and output terminals configured to receive data to be written to the array of memory cells and output data read from the array of memory cells via the plurality of bit lines
Claims20
A memory device, comprising:
- an array of memory cells, the array including a first sub array and a second sub array;
- a plurality of bit lines connected to the memory cells;
- an IO block situated between the first sub array and the second sub array, wherein the bit lines extend from the first and second memory sub arrays of the memory device directly to the IO block, and wherein the IO block includes data input and output terminals configured to receive data to be written to the array of memory cells and output data read from the array of memory cells via the plurality of bit lines.
A memory input/output (IO), comprising:
- an IO block having a first side and a second side opposite the first side, the first side configured to receive a first plurality of bit lines from a first memory sub array, the second side configured to receive a second plurality of bit lines from a second memory sub array;
- the IO block including an output latch coupled to receive data read from the first plurality and the second plurality of bit lines;
- and
- the IO block including data input and output terminals configured to receive and output data to and from the first plurality of bit lines and the second plurality of bit lines.
A memory input/output (IO) method, comprising:
- providing an array of memory cells;
- positioning an IO block so as to divide the array of memory cells into a first sub array and a second sub array situated on opposite sides of the IO block;
- receiving a first plurality of bit lines connected to the memory cells of the first sub array at a first side of the IO block;
- receiving a second plurality of bit lines connected to the memory cells of the second sub array at a second side of the IO block;
- operating the IO block to read data from the memory cells of the first and second sub arrays;
- and
- operating the IO block to write data to the memory cells of the first and second sub arrays.
Dependencies are inferred from the claim text.