Semiconductor memory device and method of operating the semiconductor memory device
AssigneeSK hynix Inc.
InventorsHee Youl LEE, Ji Hyun SEO
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device may include a memory cell array, a peripheral circuit, and a control logic circuit. The memory cell array may include a plurality of memory cells, each of which is capable of storing a plurality of bits of data. The peripheral circuit may drive the memory cell array. The control logic circuit may control the peripheral circuit to perform a first program operation on target memory cells, among the plurality of memory cells, coupled to a target word line based on first partial data, and then perform a second program operation on the target memory cells based on second partial data received after the first program operation is completed.
Claims20
A semiconductor memory device comprising:
- a memory cell array comprising a plurality of memory cells, each memory cell of which is configured to store a plurality of bits of data;
- a peripheral circuit configured to drive the memory cell array;
- and
- a control logic circuit configured to control the peripheral circuit to perform a first program operation on target memory cells of the plurality of memory cells based on first partial data, and to perform a second program operation on the target memory cells based on second partial data received after the first program operation is completed, wherein the target memory cells are coupled to a target word line.
A method of operating a semiconductor memory device including a plurality of memory cells, the method comprising:
- receiving first partial data;
- performing a first program operation on selected memory cells of the plurality of memory cells based on the first partial data;
- receiving second partial data;
- and
- performing a second program operation on the selected memory cells based on the first partial data and the second partial data.
A method of operating a semiconductor memory device to program N pages of data to a plurality of memory cells coupled to a target word line, wherein N is a natural number of at least 2, the method comprising:
- receiving first partial data including first to k-th page data, wherein k is a natural number of at least 1 and less than N;
- performing a first program operation on the plurality of memory cells coupled to the target word line based on the first partial data;
- receiving second partial data comprising (k+1)-th to N-th page data;
- and
- performing a second program operation on the plurality of memory cells coupled to the target word line based on the first partial data and the second partial data.
Dependencies are inferred from the claim text.