US 2019/0295653 A1 · MEMORY BLOCK SELECT CIRCUITRY INCLUDING VOLTAGE BOOTSTRAPPING CONTROL

Abstract

Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first memory cell string; a second memory cell string; a first group of conductive lines to access the first and second memory cell strings; a second group of conductive lines; a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and a circuit including a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor including a gate coupled to the second node, and a third transistor coupled between the second node and the common gate.

Claims16

Dependent claims

1-7. (canceled)

An apparatus comprising:

a group of semiconductor structures located in different levels of the apparatus and over a substrate;
a pillar extending through the group of semiconductor structures, the pillar being part of a memory cell string;
a group of conductive structures located over the group of semiconductor structures, the group of conductive structures being electrically separated from the group of semiconductor structures;
a capacitor including a first conductive plate formed from part of a first conductive structure of the group of conductive structures, and second conductive plate formed from part of a second conductive structure of the group of conductive structures;
a first conductive path coupled between the first conductive plate of the capacitor and a first node;
a second conductive path coupled between the second conductive plate of the capacitor and a second node;
a first transistor and a second transistor coupled in series between a third node and a fourth node, the first transistor including a gate coupled to the fourth node;
and
a third transistor coupled between the fourth node and the second node.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application

15/933,087Filed 22 Mar 2018

Published

26 Sep 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification14 codes

G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits
G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/40
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the peripheral circuit region

Memory block select circuitry including voltage bootstrapping control

Life of this patent

Memory block select circuitry including voltage bootstrapping control

Life of this patent

Abstract

Claims16