Memory device and memory system having the same
AssigneeSK hynix Inc.
InventorWon Sun PARK
Life of this patent
Estimating the term…
Abstract
The memory device includes: an independent circuit configured to output an independent signal; a memory cell array formed on a top of the independent circuit, the memory cell array including a plurality of memory cells in which data is stored; a revision circuit formed on a top of the memory cell array, the revision circuit storing modified ROM data different from the independent signal, the revision circuit outputting a ROM control signal and the modified ROM data in response to a select signal when an error occurs in the independent signal in a test operation of the independent circuit formed under the memory cell array; and a selection circuit configured to output the independent signal or the modified ROM data in response to the ROM control signal.
Claims21
A memory device comprising:
- an independent circuit configured to output an independent signal;
- a memory cell array formed on a top of the independent circuit, the memory cell array including a plurality of memory cells in which data is stored;
- a revision circuit formed on a top of the memory cell array, the revision circuit storing modified ROM data different from the independent signal, the revision circuit outputting a ROM control signal and the modified ROM data in response to a select signal when an error occurs in the independent signal in a test operation of the independent circuit formed under the memory cell array;
- and
- a selection circuit configured to output the independent signal or the modified ROM data in response to the ROM control signal.
A memory device comprising:
- operating circuits formed on a top of a substrate;
- an independent circuit formed on a top of the operating circuits, the independent circuit outputting an independent signal;
- a selection circuit formed on the top of the operating circuits, the selection circuit outputting the independent signal or modified ROM data in response to a ROM control signal;
- a memory cell array formed on a top of a NAND ROM and the selection circuit;
- and
- a revision circuit formed on a top of the memory cell array, the revision circuit transmitting the modified ROM data to the selection circuit in response to a select signal.
A memory system comprising:
- a memory device configured to store user data and output an independent signal;
- and
- a memory controller configured to transmit a modification command to the memory device to modify and output the independent signal,
- wherein the memory device includes:
- a memory cell array configured to store the user data;
- an independent circuit formed on a bottom of the memory cell array, the independent circuit outputting the independent signal;
- a revision circuit formed on a top of the memory cell array, the revision circuit storing modified ROM data different from the independent signal, the revision circuit outputting a ROM control signal and the modified ROM data in response to a select signal;
- and
- a selection circuit configured to output the independent signal or the modified ROM data in response to the ROM control signal.
Dependencies are inferred from the claim text.