Compact non-volatile memory device
AssigneeSTMicroelectronics (Rousset) SAS
InventorJulien Delalleau
Life of this patent
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Abstract
A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.
Claims20
A method of fabricating a non-volatile memory cell, the method comprising:
- forming a selection transistor that comprises an insulated selection gate embedded in a semiconducting substrate region;
- forming a semiconducting source region in contact with a lower part of the insulated selection gate;
- and
- forming a state transistor that comprises a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate, wherein the source region, the drain region, the substrate region, and the control gate are individually polarizable.
A method of fabricating a semiconductor device, the method comprising:
- forming a trench in a semiconductor substrate;
- partially filling the trench with a first conductive material, the first conductive material being electrically insulated from the semiconductor substrate by a first insulating layer;
- forming a second conductive material over the semiconductor substrate and within the trench overlying the first conductive material, the second conductive material being electrically isolated from the first conductive material by a second insulating layer;
- etching trenches within the second conductive material;
- and
- forming a third conductive material over the second conductive material and within the trenches in the second conductive material, the second conductive material being electrically isolated from the second conductive material by a third insulating layer.
A method of fabricating a semiconductor device, the method comprising:
- forming a trench in a semiconductor substrate;
- forming a first insulating layer within the trench;
- depositing a first polysilicon layer over the semiconductor substrate and filling the trench;
- etching the first polysilicon layer so that the trench is only partially filled with polysilicon;
- growing an oxide layer over the first polysilicon layer to form a second insulating layer within the trench;
- depositing a second polysilicon layer over the semiconductor substrate and over the second polysilicon layer within the trench, the second polysilicon layer filling an upper portion of the trench over the oxide layer;
- etching trenches in the second polysilicon layer so that a polysilicon block remains over the oxide layer;
- forming a third insulating layer over the polysilicon block and within the trenches in the second polysilicon layer;
- and
- depositing a third polysilicon layer over the second insulating layer and filling the trenches in the second polysilicon layer.
Dependencies are inferred from the claim text.