System And Method For Managing Peak Power Demand And Noise In Non-volatile Memory Array

A memory device, comprising:

• a plurality of memory cells arranged in rows and columns;
• a plurality of word lines each connected to a row of the memory cells;
• a plurality of bit lines each connected to a column of the memory cells;
• a word line driver connected to the word lines;
• a bit line driver connected to the bit lines;
• a plurality of word line switches each disposed on one of the word lines for selectively connecting and disconnecting one of the rows of memory cells to and from the word line driver;
• and
• a controller configured to control the plurality of word line switches to connect some but not all of the rows of memory cells to the word line driver at a first point in time.

A memory device, comprising:

• a plurality of memory cells arranged in rows and columns;
• a plurality of word lines each connected to a row of the memory cells;
• a plurality of bit lines each connected to a column of the memory cells;
• a word line driver connected to the word lines;
• a bit line driver connected to the bit lines;
• a plurality of bit line switches each disposed on one of the bit lines for selectively connecting and disconnecting one of the columns of memory cells to and from the bit line driver;
• and
• a controller configured to control the plurality of bit line switches to connect some but not all of the columns of memory cells to the bit line driver at a first point in time.

A method of operating a memory device that includes:

• a plurality of memory cells arranged in rows and columns,
• a plurality of word lines each connected to a row of the memory cells,
• a plurality of bit lines each connected to a column of the memory cells,
• a word line driver connected to the word lines,
• a bit line driver connected to the bit lines,
• a plurality of word line switches each disposed on one of the word lines for selectively connecting and disconnecting one of the rows of memory cells to and from the word line driver, and
• a plurality of bit line switches each disposed on one of the bit lines for selectively connecting and disconnecting one of the columns of memory cells to and from the bit line driver;
• the method comprising:
• operating the plurality of word line switches to connect some but not all of the rows of memory cells to the word line driver at a first point in time, and
• operating the plurality of bit line switches to connect some but not all of the columns of memory cells to the bit line driver at a second point in time.