Semiconductor memory device

Abstract

According to one embodiment, a semiconductor memory device includes a word line, a bit line crossing the word line, a memory cell, and a controller. The memory cell is provided at an intersection between the word and bit lines and includes a variable resistive element. The controller controls a voltage application and a read operation to the memory cell. The controller performs a first operation of applying a first voltage to the memory cell, and a first verification of verifying whether a resistance of the memory cell becomes equal to a first value or greater after the first operation. The controller performs a second operation of applying to the memory cell a second voltage set based on the first voltage, when the resistance of the memory cell becomes equal to the first value or greater in the first verification.

Dependencies are inferred from the claim text.