Non-volatile memory device with switchable reading mode and related reading method

A method for reading a memory device comprising a first sector and a second sector of an array of memory cells, each of the first sector and the second sector comprising a respective selector and a phase-change element configured to have a first value of resistance or a second value of resistance associated to corresponding logic data;

• the first sector comprising:
• a first top memory cell and a second top memory cell, coupled to a top wordline and, respectively, to a first top local bitline and a second top local bitline;
• and
• a first top main bitline and a second top main bitline coupled, respectively, to the first and second top local bitlines;
• the second sector comprising:
• a first bottom memory cell and a second bottom memory cell coupled to a bottom wordline and, respectively, to a first bottom local bitline and a second bottom local bitline;
• and
• a first bottom main bitline and a second bottom main bitline coupled, respectively, to the first and second bottom local bitlines;
• the memory device further comprising a reading circuit arranged between the first and second sectors and including a top reading stage comprising a first top input node and a second top input node, and a bottom reading stage comprising a first bottom input node and a second bottom input node, the memory device further comprising:
• a top circuitry configured to be controlled so as to charge the first and second top input nodes and couple the first and second top input nodes respectively to the first and second top memory cells, respectively through the first top local bitline and the first top main bitline, and through the second top local bitline and the second top main bitline;
• a bottom circuitry configured to be controlled so as to charge the first and second bottom input nodes and couple the first and second bottom input nodes respectively to the first and second bottom memory cells, respectively through the first bottom local bitline and the first bottom main bitline, and through the second bottom local bitline and the second bottom main bitline;
• a reference generator configured to be driven so as to couple to the first input node or the second top input nodes or else to the first bottom input nodes or the second bottom input node;
• the top reading stage comprising:
• a top sense amplifier comprising a first input, a second input, a first top branch, and a second top branch, the first top branch being arranged between the first input of the top sense amplifier and a first top internal node and comprising a first top inverter and a first top compensation capacitor coupled together, the second top branch being arranged between the second input of the top sense amplifier and a second top internal node and comprising a second top inverter and a second top compensation capacitor coupled together, the top sense amplifier further comprising a first top routing switch arranged between the second top internal node and the first input of the top sense amplifier, and a second top routing switch arranged between the first top internal node and the second input of the top sense amplifier;
• a first top coupling capacitor, coupled to the first input of the top sense amplifier and to a first top intermediate node;
• a second top coupling capacitor, coupled to the second input of the top sense amplifier and to a second top intermediate node;
• a first top coupling switch and a second top coupling switch configured to be controlled so as to couple, respectively, the first and second top intermediate nodes to the first and second top input nodes, respectively, and a top reading switch configured to be controlled so as to couple together the first and second top intermediate nodes;
• the bottom reading stage comprising:
• a bottom sense amplifier comprising a respective first input, a respective second input, a first bottom branch, and a second bottom branch, the first bottom branch being arranged between the first input of the bottom sense amplifier and a first bottom internal node and including a first bottom inverter and a first bottom compensation capacitor coupled together, the second bottom branch being arranged between the second input of the bottom sense amplifier and a second bottom internal node and including a second bottom inverter and a second bottom compensation capacitor coupled together, the bottom sense amplifier further comprising a first bottom routing switch arranged between the second bottom internal node and the first input of the bottom sense amplifier, and a second bottom routing switch arranged between the first bottom internal node and the second input of the bottom sense amplifier;
• a first bottom coupling capacitor coupled to the first input of the bottom sense amplifier and to a first bottom intermediate node;
• a second bottom coupling capacitor coupled to the second input of the bottom sense amplifier and to a second bottom intermediate node;
• and
• a first bottom coupling switch and a second bottom coupling switch configured to be controlled so as to couple, respectively, the first and second bottom intermediate nodes to the first bottom input node and to the second bottom input node, respectively, and a bottom reading switch configured to be controlled so as to couple together the first and second bottom intermediate nodes;
• the memory device further comprising:
• a first additional switch arranged between the first top internal node and the second input of the bottom sense amplifier;
• a second additional switch arranged between the second top internal node and the first input of the bottom sense amplifier;
• a third additional switch arranged between the first bottom internal node and the second input of the top sense amplifier;
• a fourth additional switch arranged between the second bottom internal node and the first input of the top sense amplifier;
• and
• a fifth additional switch arranged between the first top intermediate node and the second bottom intermediate node;
• the reading method comprising executing a first set of operations comprising driving the first, second, third, and fourth additional switches so as to decouple the top sense amplifier and the bottom sense amplifier, and executing a first group of operations or a second group of operations, the first group of operations comprising:
• driving the first and second top routing switches so as to couple the first and second top branches and form a first loop circuit;
• selecting the top wordline and driving the top circuitry so as to discharge the first and second top input nodes by currents that flow, respectively, in the first and second top memory cells and that depend upon the values of resistance of the respective phase-change elements;
• and
• driving the first and second top coupling switches so as to discharge the first and second top coupling capacitors as a function of discharge, respectively, of the first and second top input nodes, and subsequently driving the top reading switch so as to couple together the first and second top intermediate nodes and cause evolution of the first loop circuit into a respective first condition of equilibrium or second condition of equilibrium, as a function of a difference of charge present between the first and second top coupling capacitors;
• and wherein the second group of operations comprises:
• driving the first and second bottom routing switches so as to couple the first and second bottom branches and form a second loop circuit;
• selecting the bottom wordline and driving the bottom circuitry so as to discharge the first and second bottom input nodes by currents that flow, respectively, in the first and second bottom memory cells and depend upon the values of resistance of the respective phase-change elements;
• and
• driving the first and second bottom coupling switches so as to discharge the first and second bottom coupling capacitors as a function of discharge, respectively, of the first and second bottom input nodes, and subsequently driving the bottom reading switch so as to couple together the first and second bottom intermediate nodes and cause evolution of the second loop circuit into a respective first condition of equilibrium or second condition of equilibrium, as a function of a difference of charge present between the first and second bottom coupling capacitors;
• the reading method further comprising executing at least one second set of operations comprising driving the first and second top routing switches so as to decouple the first and second top branches, driving the first and second bottom routing switches so as to decouple the first and second bottom branches, and executing a third group of operations comprising:
• driving the first and fourth additional switches so as to couple the first top branch and the second bottom branch and form a third loop circuit;
• selecting the top wordline and driving the top circuitry so as to discharge the first top input node by the current that flows in the first top memory cell and that depends upon the value of resistance of the respective phase-change element;
• driving the bottom circuitry so as to couple the second bottom input node to the second bottom local bitline and to the second bottom main bitline;
• deselecting the bottom wordline;
• coupling the reference generator to the second bottom input node and discharging the second bottom input node by a reference current;
• and
• driving the first top coupling switch and the second bottom coupling switch so as to discharge the first top coupling capacitor and the second bottom coupling capacitor as a function of discharge, respectively, of the first top input node and of the second bottom input node, and subsequently driving the fifth additional switch so as to couple together the first top intermediate node and the second bottom intermediate node and cause evolution of the third loop circuit into a respective first condition of equilibrium or second condition of equilibrium, as a function of a difference of charge present between the first top coupling capacitor and the second bottom coupling capacitor.