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US 2019/0295633 A1Published application
Complementary dual-modular redundancy memory cell
AssigneeBar-llan University
InventorsRobert GITERMAN, Lior ATIAS, Adam TEMAN, Alexander FISH
Life of this patent
Estimating the term…
Abstract
A CDMR memory cell, includes a first bitcell which is used to store a current data level and a second bitcell which is used to store the complementary data level. When a read operation is performed, a comparator compares the data levels read from the two bitcells. If these two levels are not complementary, the comparator outputs an indicator. This indicator serves as an alert that a storage error has, or may have, occurred.
Claims28
A memory cell, comprising:
- a data write input, configured to input data levels for storing in said memory cell;
- a data read output;
- an indicator output;
- a first bitcell connected to said data write input and said data read output, configured to store a first data level input from said data write input and to output a first read data level to said data read output;
- and
- a second bitcell connected to said data write input, configured to store a second data level input from said data write input to output a second read data level;
- and
- a comparator associated with said first bitcell, said second bitcell and said indicator output, configured to compare a data level read from said first bitcell and a data level read from said second bitcell and to provide, at said indicator output, an indicator when said first read data level and said second read data level are non-complementary.
5 more elements
A memory array comprising:
- a data write input port, configured to input data levels for storing in said array;
- a data read output port, configured to output data levels from said memory array;
- an indicator output port;
- a plurality of memory cells, each of said memory cells comprising:
- a first bitcell connected to said data write input port and said data read output port, configured to store first data levels and to output first read data levels;
- and
- a second bitcell connected to said data write input port, configured to store second data levels and to output a second read data levels;
- and
- at least one comparator, configured to compare respective first and second read data levels a selected memory cell and to provide, at said indicator output port, a respective indicator when said first read data level and said second read data level are non-complementary.
6 more elements
A method comprising:
- providing a memory cell comprising:
- a first bitcell configured to store a first input data level and to output said stored first data level to a data read output;
- and
- a second bitcell configured to store a second input data level;
- storing a first data level in said first bitcell and a complementary data level in said second bitcell;
- reading first and second data levels from said first and second bitcells respectively;
- and
- providing an indicator when first and second read data levels are non-complementary.
5 more elements
Dependencies are inferred from the claim text.