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US 2019/0295630 A1Published application
Memory circuit configuration and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorShih-Lien Linus LU
Life of this patent
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Abstract
A circuit includes a data line, a first cell in a first row of a memory array, and a second cell in a second row of the memory array. The first cell is electrically coupled with the data line and the second cell is electrically coupled with the data line. The circuit is configured to simultaneously transfer data from the first cell and the second cell to the data line in a first read operation on the first row.
Claims20
A circuit comprising:
- a data line;
- a first cell in a first row of a memory array, the first cell electrically coupled with the data line;
- and
- a second cell in a second row of the memory array, the second cell electrically coupled with the data line,
- wherein the circuit is configured to bias the data line by summing a current of the first cell with a current of the second cell, thereby simultaneously transferring data from the first cell and the second cell to the data line in a first read operation on the first row.
2 more elements
A method of reading data from a weak cell, the method comprising:
- receiving an address signal including address information corresponding to an address of a first row of a memory array, the first row of the memory array including the weak cell;
- and
- responsive to the receiving the address signal including the address information:
- reading a data bit from the weak cell;
- and
- simultaneously reading a matching data bit from a cell in a second row of the memory array.
3 more elements
A method of configuring a memory circuit, the method comprising:
- identifying a weak row of cells of the memory circuit based on a speed of a test read operation on the weak row meeting a first speed criterion;
- storing address information corresponding to an address of the weak row in a storage device;
- and
- during subsequent read operations on the weak row, simultaneously reading data from the weak row and from a second row of cells of the memory circuit based on the stored address information.
1 more element
Dependencies are inferred from the claim text.