US 2019/0295624 A1 · SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR SYSTEM RELATED TO PERFORMING A RESET OPERATION

Abstract

A semiconductor package for performing a reset operation includes a first semiconductor device including a first resistor element coupled to a reset pin, the first semiconductor device configured to be applied with a reset signal through the reset pin such that the reset operation is performed. The semiconductor package includes a second semiconductor device including a second resistor element coupled to the reset pin, the second semiconductor device configured to be applied with the reset signal through the reset pin such that the reset operation is performed. The first resistor element and the second resistor element may be selectively coupled to the reset pin when the reset operation is performed.

Claims24

Dependent claims

A semiconductor package for performing a reset operation, comprising:

a first semiconductor device including a first resistor element coupled to a reset pin, the first semiconductor device configured to be applied with a reset signal through the reset pin such that the reset operation is performed;
and
a second semiconductor device including a second resistor element coupled to the reset pin, the second semiconductor device configured to be applied with the reset signal through the reset pin such that the reset operation is performed,
wherein the first resistor element and the second resistor element are selectively coupled to the reset pin when the reset operation is performed.

1 more element

A semiconductor system for performing a reset operation, comprising:

a controller configured to output a power supply voltage, a reset signal, and first and second switch control signals;
and
a semiconductor package including a first semiconductor chip, a second semiconductor chip, and a reset pin, the first semiconductor chip including a first reset processing circuit configured to perform the reset operation by receiving the power supply voltage, the reset signal, and the first switch control signal, the second semiconductor chip including a second reset processing circuit configured to perform the reset operation by receiving the power supply voltage, the reset signal, and the second switch control signal, and the reset pin being coupled to one of a resistor element included in the first reset processing circuit or a resistor element included in the second reset processing circuit, based on the first switch control signal and the second switch control signal.

A semiconductor system for performing a reset operation, comprising:

a controller configured to output a power supply voltage, a reset signal, first to fourth power switch control signals, and first to fourth switch control signals;
and
a semiconductor package including a first semiconductor chip, a second semiconductor chip, and a reset pin, the first semiconductor chip including a first reset processing circuit configured to perform the reset operation by receiving the power supply voltage, the reset signal, the first and second power switch control signals, and the first and second switch control signals, the second semiconductor chip including a second reset processing circuit configured to perform the reset operation by receiving the power supply voltage, the reset signal, the third and fourth power switch control signals, and the third and fourth switch control signals, and the reset pin being coupled to one among first and second resistor elements included in the first reset processing circuit and third and fourth resistor elements included in the second reset processing circuit, based on the first to fourth power switch control signals and the first to fourth switch control signals.

A semiconductor system for performing a reset operation, comprising:

a controller configured to output a power supply voltage, a reset signal, and first to fourth switch control signals;
and
a multi-chip package including a first semiconductor package, a second semiconductor package, and a reset pin, the first semiconductor package including a first semiconductor chip and a second semiconductor chip, the second semiconductor package including a third semiconductor chip and a fourth semiconductor chip, the first semiconductor chip including a first reset processing circuit configured to perform the reset operation by receiving the power supply voltage, the reset signal, and the first switch control signal, the second semiconductor chip including a second reset processing circuit configured to perform the reset operation by receiving the power supply voltage, the reset signal, and the second switch control signal, the third semiconductor chip including a third reset processing circuit configured to perform the reset operation by receiving the power supply voltage, the reset signal and the third switch control signal, the fourth semiconductor chip including a fourth reset processing circuit configured to perform the reset operation by receiving the power supply voltage, the reset signal and the fourth switch control signal, and the reset pin being coupled to one of resistor elements included in the first to fourth reset processing circuits, based on the first to fourth switch control signals.

Dependencies are inferred from the claim text.

Semiconductor package and semiconductor system related to performing a reset operation

Life of this patent

Semiconductor package and semiconductor system related to performing a reset operation

Life of this patent

Abstract

Claims24