Register file bit cells with integrated multiplexer
AssigneeOracle International Corporation
InventorRobert Weisenbach
Life of this patent
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Abstract
A bit cell structure with an integrated multiplexer is disclosed. In one embodiment, a circuit includes a plurality of bit cells, e.g., first and second bit cells. The circuit further includes a multiplexer having an input coupled to a first data line associated with the first bit cell and a second input coupled to a second data line associated with a second bit cell. The circuit further includes a PMOS transistor having a gate terminal coupled to an output of the multiplexer, and further coupled between a local read bit line and a voltage source. The PMOS transistor is configured to pull the local read bit line to a logic high value responsive to a selected one of the plurality of bit cells conveying a logic low to its respectively coupled input of the multiplexer.
Claims20
A circuit comprising:
- a first bit cell and a second bit cell;
- a multiplexer having a first input coupled to a first data line associated with the first bit cell, and a second input coupled to a second data line associated with the second bit cell;
- and
- a first PMOS (p-channel metal oxide semiconductor) transistor having a gate terminal coupled to an output of the multiplexer, and further coupled between a local read bit line and a voltage source, wherein the first PMOS transistor is configured to pull the local read bit line to a logic high value responsive to a selected one of the first and second bit cells conveying a logic low value to its respectively coupled input of the multiplexer.
A method comprising:
- storing respective logic values in each of a first bit cell and a second bit cell;
- selecting, using a multiplexer, one of a first input coupled to a first a first data line associated with the first bit cell and a second input coupled to a second data line associated with the second bit cell;
- and
- providing, from an output of the multiplexer to a gate terminal of a first PMOS (p-channel metal oxide semiconductor) transistor, wherein the first PMOS transistor is configured to pull a local read bit line to a logic high value responsive to a selected one of the first and second bit cells conveying a logic low value to its respectively coupled input of the multiplexer.
A register file comprising:
- a plurality of bit cells;
- a multiplexer having a plurality of inputs, wherein each of the plurality of inputs is coupled to a data line of a corresponding one of the plurality of bit cells;
- and
- a first PMOS (p-channel metal oxide semiconductor) transistor having a gate terminal coupled to an output of the multiplexer, and further coupled between a local read bit line and a voltage source, wherein the first PMOS transistor is configured to pull the local read bit line to a logic high value responsive to a selected one of the plurality of bit cells conveying a logic low value to its respectively coupled input of the multiplexer.
Dependencies are inferred from the claim text.