Device having multiple channels with calibration circuit shared by multiple channels

An apparatus comprising:

• a semiconductor memory device of a single semiconductor chip including a first channel and a second channel provided independently of the first channel;
• wherein the first channel includes a plurality of first external terminals, a first command control circuit coupled to at least one of the plurality of the first external terminals, a first memory cell array configured to be controlled by the first command control circuit and a first data output circuit configured to output first data from the first memory cell array with first impedance controlled responsive to a first calibration code;
• wherein the second channel includes a plurality of second external terminals, a second command control circuit coupled to at least one of the plurality of the second external terminals, a second memory cell array configured to be controlled by the second command control circuit and a second data output circuit configured to output second data from the second memory cell array with second impedance controlled responsive to a second calibration code;
• and
• wherein a calibration circuit provided in common to the first channel and the second channel to provide the first calibration code responsive to a first calibration control signal from the first command control circuit and a second calibration code responsive to a second calibration control signal from the second command control circuit.

A method comprising:

• receiving at a semiconductor memory device of a single semiconductor chip, a first calibration command to adjust an impedance of a first output circuit in a first channel of the semiconductor memory device, wherein the semiconductor memory device comprises the first channel and a second channel provided independently of the first channel to which mutually different external terminals including clock, data and command/address terminals are allocated;
• performing a first calibration operation responsive to the first calibration command;
• receiving a second calibration command to adjust impedance of a second output circuit in the second channel;
• ignoring the second calibration command when the second calibration command has been received while the first calibration operation is being performed;
• receiving a first latch command in the first channel;
• supplying a first calibration code produced by the first calibration operation to the first output circuit in the first channel responsive to the first latch command, causing the first output circuit to change impedance responsive to at least a portion of the first calibration code;
• and
• supplying the first calibration code to the second output circuit, causing the second output circuit to change impedance responsive to at least a portion of the first calibration code.