Power Management Integrated Circuit with Dual Power Feed
AssigneeMicron Technology, Inc.
InventorMatthew David Rowley
Life of this patent
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Abstract
A power management integrated circuit (PMIC) receives power from a host and a backup power supply in parallel and uses power from at least one of the host and the backup power supply to operate voltage regulators for a memory system. An enable signal is generated based on whether or not the voltage regulators are powered. The enable signal can be used to keep the backup power supply on while the memory system is in operation. In response to absence of power from the host, the PMIC generates an interrupt signal causing the memory system to shut down safely without data loss.
Claims20
A power management integrated circuit, comprising:
- a first power input;
- a second power input;
- and
- at least one voltage regulator operable to generate voltages for a memory system;
- a sequencer configured to control one or more sequences of power events in the power management integrated circuit;
- and
- a circuit configured to combine the first power input and the second power input to power the at least one voltage regulator.
A system, comprising:
- a non-volatile memory device;
- and
- a power management integrated circuit comprising:
- at least one voltage regulator configured to generate operating voltages for the non-volatile memory device;
- a first pin to receive power from a first power source;
- a second pin to receive power from a second power source;
- and
- a circuit configured to combine the first pin and the second pin to power the at least one voltage regulator.
A method, comprising:
- receiving power, from a first power source, in a first pin of a power management integrated circuit;
- receiving power, from a second power source, in a second pin of the power management integrated circuit;
- combining, in the power management integrated circuit, power from the first pin and power from the second pin to generate a combined power input;
- and
- powering at least one voltage regulator of the power management integrated circuit using the combined power input to generate voltages for a memory device.
Dependencies are inferred from the claim text.