Apparatuses and methods for power efficient driver circuits

An apparatus comprising:

• first, second and third voltage lines configured to receive first, second and third voltages, respectively;
• a plurality of first transistors, each of the plurality of first transistors being coupled between the first voltage line and an output node and configured to receive an associated one of a plurality of first enable signals;
• a plurality of second transistors, each of the plurality of second transistors being coupled between the second voltage line and the output node and configured to receive an associated one of a plurality of second enable signals;
• and
• a plurality of third transistors, each of the plurality of third transistors being coupled between the third voltage line and the output node and configured to receive an associated one of a plurality of third enable signals,
• wherein the plurality of third enable signals are different from the plurality of first enable signals and the plurality of second enable signals.

A method comprising:

• selectively providing a first plurality of enable signals to respective gates of a first set of transistors, and a second plurality of enable signals to respective gates of a second set of transistors;
• driving an output signal with the first set of transistors coupled to a first voltage based on the first plurality of enable signals received at the respective gates of the first set of transistors;
• and
• driving the output signal with the second set of transistors coupled to a second voltage based on the second plurality of enable signals received at the respective gates of the second set of transistors.