Stacked dram device and method of manufacture
AssigneeRambus Inc.
InventorThomas Vogelsang
Life of this patent
Estimating the term…
Abstract
A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.
Claims21
(canceled)
A memory device comprising:
- a first integrated circuit (IC) memory chip including
- first memory core circuitry, and
- first input/output (I/O) circuitry electrically coupled to the first memory core circuitry;
- a second IC memory chip vertically stacked with the first IC memory chip, the second IC memory chip including
- second memory core circuitry, and
- second I/O circuitry decoupled from the second memory core circuitry;
- and
- wherein data transfers involving the second memory core circuitry and an off-chip memory controller bypass the second I/O circuitry and are routed to the first I/O circuitry.
A memory module, comprising:
- a substrate;
- multiple memory devices mounted to the substrate, each memory device comprising
- multiple dynamic random access memory (DRAM) integrated circuit (IC) chips stacked in a vertical relationship, each of the multiple DRAM IC chips including
- memory core circuitry, and
- input/output (I/O) circuitry;
- and
- wherein data transfers involving a first one of the multiple DRAM IC chips and an off-chip memory controller are routed to the I/O circuitry of the first one of the multiple DRAM IC chips via a conductive path;
- and
- wherein data transfers involving a second one of the multiple DRAM IC chips and an off-chip memory controller bypass the I/O circuitry of the second one of the multiple DRAM IC chips and are routed to the I/O circuitry of the first one of the multiple DRAM IC chips.
A memory, comprising:
- at least one memory module including
- a substrate;
- multiple memory devices mounted to the substrate, each memory device comprising
- multiple dynamic random access memory (DRAM) integrated circuit (IC) chips stacked in a vertical relationship, each of the multiple DRAM IC chips including
- memory core circuitry, and
- input/output (I/O) circuitry;
- and
- wherein data transfers involving a first one of the multiple DRAM IC chips and an off-chip memory controller are routed to the I/O circuitry of the first one of the multiple DRAM IC chips via a conductive path;
- and
- wherein data transfers involving a second one of the multiple DRAM IC chips and an off-chip memory controller bypass the I/O circuitry of the second one of the multiple DRAM IC chips and are routed to the I/O circuitry of the first one of the multiple DRAM IC chips.
Dependencies are inferred from the claim text.