Semiconductor memory device
AssigneeToshiba Memory Corporation
InventorJumpei SATO
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes n interconnect layers above a substrate; and a first interconnect region between an end of a control circuit and an end of the substrate in a direction of a first axis beside a first pad region in a direction of a second axis. The n interconnect layers are located at different levels from the substrate. Each of the n interconnect layers includes an interconnect. The first interconnect region includes no transistor, and no contact coupled to the substrate. The first interconnect region includes an interconnect extending along the second axis in m (m is a natural number equal to or larger than 3, larger than n/2, and equal to or smaller than n) interconnect layers of the n interconnect layers.
Claims15
A semiconductor memory device comprising:
- a substrate;
- a control circuit on the substrate, the control circuit comprising a transistor;
- a first pad region comprising a pad above the substrate;
- n (n is a natural number equal to or larger than 3) interconnect layers above the substrate, the n interconnect layers being located at different levels from the substrate, each of the n interconnect layers comprising an interconnect;
- and
- a first interconnect region between an end of the control circuit and an end of the substrate in a direction of a first axis beside the first pad region in a direction of a second axis, the first interconnect region comprising no transistor, the first interconnect region comprising no contact coupled to the substrate, and the first interconnect region comprising an interconnect extending along the second axis in m (m is a natural number equal to or larger than 3, larger than n/2, and equal to or smaller than n) interconnect layers of the n interconnect layers.
Dependencies are inferred from the claim text.