Semiconductor memory device
AssigneeSK hynix Inc.
InventorsJin-Ho KIM, Sung-Lae OH
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Abstract
A semiconductor memory device includes a plurality of pass transistors disposed along a first direction over a substrate, and configured to transfer operating voltages to a memory cell array; and a plurality of global lines formed in a first wire layer over the pass transistors, extending in a second direction intersecting with the first direction, and configured to transfer the operating voltages to the corresponding pass transistors respectively. The global lines are disposed in first direction pitches of some pass transistors among the pass transistors.
Claims20
A semiconductor memory device comprising:
- a plurality of pass transistors disposed along a first direction over a substrate, and configured to transfer operating voltages to a memory cell array;
- and
- a plurality of global lines formed in a first wire layer over the pass transistors, extending in a second direction intersecting with the first direction, and configured to transfer the operating voltages to the corresponding pass transistors respectively,
- wherein the global lines are disposed in only some pass transistors pitches in the first direction.
A semiconductor memory device comprising:
- a plane disposed over a substrate, and including a memory cell array and a row decoder;
- and
- a peripheral circuit disposed adjacent to the plane in a second direction intersecting with a first direction, over the substrate,
- the row decoder comprising
- a plurality of pass transistors disposed along the first direction, and configured to transfer operating voltages to the memory cell array;
- and
- a plurality of global lines formed in a first wire layer over the pass transistors, extending in the second direction, and configured to transfer the operating voltages to the corresponding pass transistors respectively,
- wherein the global lines are disposed in first direction pitches of some pass transistors among the pass transistors, and are not disposed in first direction pitches of remaining pass transistors.
A semiconductor memory device comprising:
- a plurality of pass transistors disposed along a first direction over a substrate, and configured to transfer operating voltages to a memory cell array;
- and
- a plurality of global lines formed in a first wire layer over the pass transistors, extending in a second direction intersecting with the first direction, and configured to transfer the operating voltages to the corresponding pass transistors respectively,
- wherein a first direction pitch of the global lines smaller than a first direction pitch of the pass transistors.
Dependencies are inferred from the claim text.