Shift register, driving method, gate driving circuit, and display device

A shift register comprising:

• an input circuit, respectively coupled to a signal input terminal, a first clock signal terminal, a second clock signal terminal, a first power terminal and a second power terminal, and the input circuit being configured to transmit a first signal from the first power terminal or a second signal from the second power terminal to an output control circuit under control of an input signal, a first clock signal and a second clock signal;
• and
• the output control circuit, respectively coupled to the input circuit, the first clock signal terminal, the second clock signal terminal, the first power terminal, the second power terminal, and a signal output terminal, the output control circuit being configured to transmit the first signal from the first power terminal or the second signal from the second power terminal to the signal output terminal under control of the first clock signal and the second clock signal,
• wherein the input signal input to the shift register is delayed and output to a signal input terminal of a shift register in a next row.