Display device and electronic shelf label
AssigneeJapan Display Inc.
InventorTatsuya Ishii
Life of this patent
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Abstract
According to an aspect, a display device includes a plurality of sub-pixels arranged in a row direction and a column direction, and each including a memory block that has at least one memory configured to store sub-pixel data. The at least one memory includes: a first transistor including a first floating gate and configured to store the sub-pixel data based on an electric charge in the first floating gate; and a second transistor including a second floating gate electrically coupled to the first floating gate of the first transistor, one of a drain and a source of the second transistor being coupled to a power supply potential, the other of the drain and the source being coupled to a node. Each of the sub-pixels is configured to display an image based on a potential of the node.
Claims20
A display device comprising a plurality of sub-pixels arranged in a row direction and a column direction, and each including a memory block that has at least one memory configured to store sub-pixel data, wherein
- the at least one memory includes:
- a first transistor including a first floating gate and configured to store the sub-pixel data based on an electric charge in the first floating gate;
- and
- a second transistor including a second floating gate electrically coupled to the first floating gate of the first transistor, one of a drain and a source of the second transistor being coupled to a power supply potential, the other of the drain and the source being coupled to a node, and
- each of the sub-pixels is configured to display an image based on a potential of the node.
An electronic shelf label comprising a plurality of sub-pixels arranged in a row direction and a column direction, and each including a memory block that has at least one memory configured to store sub-pixel data, wherein
- the at least one memory includes:
- a first transistor including a first floating gate and configured to store the sub-pixel data based on an electric charge in the first floating gate;
- and
- a second transistor including a second floating gate electrically coupled to the first floating gate of the first transistor, one of a drain and a source of the second transistor being coupled to a power supply potential, the other of the drain and the source being coupled to a node, and
- each of the sub-pixels is configured to display an image based on a potential of the node.
Dependencies are inferred from the claim text.