Emission driving circuit, driving method of shift register, and display device

A display device, comprising an emission driving circuit, wherein the emission driving circuit comprises comprising a first signal line, a second signal line, and a plurality of cascaded shift registers, wherein each shift register of the plurality of cascaded shift registers comprises:

• a first node control module electrically connected to an input signal terminal, a first clock signal terminal, and a second clock signal terminal and configured to control a level state of a first node based on an input signal, a first clock signal and a second clock signal;
• a second node control module electrically connected to the input signal terminal, the first clock signal terminal, the second clock signal terminal, a high level signal terminal and the first node and configured to control a level state of a second node based on the input signal, the first clock signal, the second clock signal, a high level signal and the level state of the first node, wherein in a phase when the input signal is at a high level and the first clock signal is at a low level, a third node for controlling the level at the second node is provided with a high level, such that in a phase when the input signal is at a high level and the second clock signal is at a low level, the level at the third node is pulled down so as to provide a low level at the second node;
• and
• an output control module electrically connected to the high level signal terminal, a low level signal terminal, the first node and the second node and configured to control an output terminal to output a high level or a low level based on the level state of the first node and the level state of the second node,
• wherein shift register at each odd-numbered stage has a first clock signal terminal electrically connected to the first signal line, and a second clock signal terminal electrically connected to the second signal line, and
• wherein shift register at each even-numbered stage has a first clock signal terminal electrically connected to the second signal line, and a second clock signal terminal electrically connected to the first signal line.

A driving method of a shift register, applicable in a shift register, wherein the shift register comprises:

• a first node control module electrically connected to an input signal terminal, a first clock signal terminal, and a second clock signal terminal and configured to control a level state of a first node based on an input signal, a first clock signal and a second clock signal;
• a second node control module electrically connected to the input signal terminal, the first clock signal terminal, the second clock signal terminal, a high level signal terminal and the first node and configured to control a level state of a second node based on the input signal, the first clock signal, the second clock signal, a high level signal and the level state of the first node, wherein in a phase when the input signal is at a high level and the first clock signal is at a low level, a third node for controlling the level at the second node is provided with a high level, such that in a phase when the input signal is at a high level and the second clock signal is at a low level, the level at the third node is pulled down so as to provide a low level at the second node;
• and
• an output control module electrically connected to the high level signal terminal, a low level signal terminal, the first node and the second node and configured to control an output terminal to output a high level or a low level based on the level state of the first node and the level state of the second node,
• wherein the driving method comprises:
• in a first phase when the input signal is at the low level, the first clock signal is at the high level and the second clock signal is at the low level, providing low level at the first node, providing high level at the second node and outputting low level at the output terminal based on the low level at the first node;
• in a second phase when the input signal is at the high level, the first clock signal is at the low level and the second clock signal is at the high level, maintaining the first node at the low level in the first phase, providing the high level at the second node, outputting the low level at the output terminal and providing the high level at the third node based on the low level at the first node;
• in a third phase when the input signal is at the high level, the first clock signal is at the high level and the second clock signal is at the low level, providing the high level at the first node, pulling down the level at the third node to provide the low level at the second node and outputting the high level at the output terminal;
• in a fourth phase when the input signal is at the low level, the first clock signal is at the low level and the second clock signal is at the high level, maintaining the first node at the high level in the third phase, maintaining the second node at the low level in the third phase, outputting the high level at the output terminal and providing the high level at the third node;
• and
• in a fifth phase when the input signal is at the low level, the first clock signal is at the high level and the second clock signal is at the low level, providing the low level at the first node, providing the high level at the second node and outputting the low level at the output terminal based on the low level of the first node.