Integrated circuit layout generation method and system
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKe-Ying SU, Ke-Wei SU, Keng-Hua KUO, Lester CHANG
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Abstract
A method of generating a layout diagram of an IC device includes receiving a layout diagram of the IC device, the IC layout diagram including a gate region having a width across an active region, and a gate via positioned at a location along the width. The location is used to divide the width into a plurality of width segments, an effective resistance of the gate region is calculated based on the plurality of width segments, and the effective resistance is used to determine whether the IC layout diagram complies with a design specification.
Claims20
A method of generating a layout diagram of an integrated circuit (IC) device, the method comprising:
- receiving the layout diagram of the IC device, the IC layout diagram comprising:
- a gate region having a width across an active region;
- and
- a gate via positioned at a location along the width;
- using the location to divide the width into a plurality of width segments;
- calculating an effective resistance of the gate region based on the plurality of width segments;
- and
- using the effective resistance to determine whether the IC layout diagram complies with a design specification.
An integrated circuit (IC) layout diagram generation system comprising:
- a processor;
- and
- a non-transitory, computer readable storage medium including computer program code for one or more programs, the non-transitory, computer readable storage medium and the computer program code being configured to, with the processor, cause the system to:
- receive an IC layout diagram comprising:
- a gate region having a width across an active region;
- and
- a gate via positioned at a location along the width;
- based on the location, divide the width into a plurality of width segments;
- calculate an effective resistance of the gate region from the width segments;
- and
- perform a circuit simulation based on the effective resistance.
A method of generating a layout diagram of an integrated circuit (IC) device, the method comprising:
- receiving the layout diagram of the IC device, the IC layout diagram comprising:
- a gate region having a width across an active region;
- and
- a gate via positioned at a location along the width;
- using the location to divide the width into a plurality of width segments;
- calculating a resistance value based on a distributed resistance model applied to the plurality of width segments;
- modeling the gate region using a delta resistance network, wherein each resistor of the delta resistance network has a value based on the resistance value;
- and
- using the delta resistance network to determine whether the IC layout diagram complies with a design specification.
Dependencies are inferred from the claim text.