Clock Verification
AssigneeImagination Technologies Limited
InventorAshish DARBARI
Life of this patent
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Abstract
Methods and systems for verifying a derived clock using assertion-based verification. The method comprises counting the number of full or half cycles of a fast clock that occur between the rising edge and the falling edge of a slow clock (i.e. during the ON phase of the slow clock); counting the number of full or half cycles of the fast clock that occur between the falling edge and the rising edge of the slow clock (i.e. during the OFF phase of the slow clock); and verifying the counts using assertion-based verification.
Claims20
A method of verifying a function of a derived clock signal in an integrated circuit hardware design, the derived clock signal being derived in the integrated circuit hardware design from a reference clock signal to have a particular duty cycle and period, the method comprising:
- verifying, in a processor, the duty cycle and period of the derived clock signal by formally verifying, by a formal verification tool, that one or more assertions written in an assertion-based language are true for the integrated circuit hardware design, the one or more assertions using determined first and second numbers and one or more predetermined numbers, said first number being a number of full or half cycles of a first clock signal between a rising edge and a falling edge of a second clock signal and said second number being a number of full or half cycles of the first clock signal between a falling edge and a rising edge of the second clock signal;
- wherein the faster of the reference clock signal and the derived clock signal is designated as the first clock signal, and the slower of the reference clock signal and the derived clock signal is designated as the second clock signal.
A system to verify a function of a derived clock signal in an integrated circuit hardware design, the derived clock signal being derived in the integrated circuit hardware design from a reference clock signal to have a particular duty cycle and period, the system comprising:
- a verification system comprising:
- at least one first state machine configured to determine a first number, said first number being a number of full or half cycles of a first clock signal between a rising edge and a falling edge of a second clock signal, wherein the faster of the reference clock signal and the derived clock signal is designated as the first clock signal, and the slower of the reference clock signal and the derived clock signal is designated as the second clock signal;
- at least one second state machine configured to determine a second number, said second number being a number of full or half cycles of the first clock signal between a falling edge and a rising edge of the second clock signal;
- and
- an assertion verification unit configured to evaluate one or more assertions written in an assertion-based language that use the determined first and second numbers and one or more predetermined numbers;
- and
- a formal verification tool configured to verify the duty cycle and period of the derived clock signal by formally verifying that the one or more assertions are true for the integrated circuit hardware design.
A non-transitory computer readable storage medium having stored thereon computer executable program code that when executed causes at least one processor to, when the at least one processor is running a formal verification tool, cause the formal verification tool to verify a function of a derived clock signal in an integrated circuit hardware design, the derived clock signal being derived in the integrated circuit hardware design from a reference clock signal to have a particular duty cycle and period, the computer executable code causing the formal verification tool to:
- verify the duty cycle and period of the derived clock signal by formally verifying that one or more assertions written in an assertion-based language are true for the integrated circuit hardware design, the one or more assertions using determined first and second numbers and one or more predetermined numbers, said first number being a number of full or half cycles of a first clock signal between a rising edge and a falling edge of a second clock signal and said second number being a number of full or half cycles of the first clock signal between a falling edge and a rising edge of the second clock signal;
- wherein the faster of the reference clock signal and the derived clock signal is designated as the first clock signal, and the slower of the reference clock signal and the derived clock signal is designated as the second clock signal.
Dependencies are inferred from the claim text.