Support of Wide Single Instruction Multiple Data (SIMD) Register Vectors through a Virtualization of Multithreaded Vectors in a Simultaneous Multithreaded (SMT) Architecture

Abstract

A computing device and a method of allocating vector register files in a simultaneously-multithreaded (SMT) processor core are provided. A request for a first number (M) of vector register files is received from a borrower thread of the processor core. One or more available donor threads of the processor core are identified. A second number (N) of the vector register files, of the identified one or more available donor threads, are assigned to the borrower thread, where N is ≤M. The borrower thread is parameterized to create a virtualized vector register file for the borrower thread, based on a width of the N vector register files of the identified one or more donor threads.

Dependencies are inferred from the claim text.