High performance computing (hpc) node having a plurality of switch coupled processors

A computing node comprising:

• a first motherboard;
• at least two first processors integrated onto the first motherboard and configured to communicate with each other;
• and
• a first switch integrated onto the first motherboard, the at least two first processors communicably coupled to the first switch, the first switch configured to communicably couple the at least two first processors to second processors integrated onto a second motherboard via a second switch integrated onto the second motherboard, the second switch configured to communicably couple the second processors to the first switch and third processors integrated onto a third motherboard via a third switch integrated onto the third motherboard;
• the at least two first processors configured to communicate with the second processors on the second motherboard via the first switch and the second switch;
• and
• the at least two first processors configured to communicate with the third processors via the first switch, the second switch, and the third switch without communicating via either of the second processors.

A computing system comprising a plurality of interconnected nodes, each node of the plurality of interconnected nodes comprising:

• a first motherboard;
• at least two first processors integrated onto the first motherboard and configured to communicate with each other;
• and
• a first switch integrated onto the first motherboard, the first processors communicably coupled to the first switch, the first switch configured to communicably couple the at least two first processors to second processors integrated onto a second motherboard via a second switch integrated onto the second motherboard, the second switch configured to communicably couple the second processors to the first switch and third processors integrated onto a third motherboard via a third switch integrated onto the third motherboard;
• the at least two first processors configured to communicate with the second processors on the second motherboard via the first switch and the second switch;
• and
• the at least two first processors configured to communicate with the third processors via the first switch, the second switch, and the third switch without communicating via either of the second processors.

A method comprising:

• integrating, onto a first motherboard, at least two first processors and configuring the at least two first processors to communicate with each other;
• and
• integrating a first switch onto the first motherboard and communicably coupling (a) the at least two first processors to the first switch, (b) second processors integrated onto a second motherboard via a second switch integrated onto the second motherboard, and (c) third processors integrated onto a third motherboard via a third switch integrated onto the third motherboard;
• configuring the at least two first processors to communicate with the second processors on the second motherboard via the first switch and the second switch;
• and
• configuring the at least two first processors to communicate with the third processors via the first switch, the second switch, and the third switch without communicating via either of the second processors.