US 2019/0294571 A1Published application

Operation of a multi-slice processor implementing datapath steering

AssigneeInternational Business Machines Corporation

InventorsSTEVEN R. CARLOUGH, KURT A. FEISTE, BRIAN W. THOMPTO, PHILLIP G. WILLIAMS

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Abstract

Operation of a multi-slice processor implementing datapath steering, where the multi-slice processor includes a plurality of execution slices. Operation of such a multi-slice processor includes: identifying, from a set of instructions, a second instruction that is dependent upon a first instruction in the set of instructions; and responsive to the second instruction being dependent upon the first instruction in the set of instructions, issuing each of the instructions in the set of instructions to a particular set of execution slices configured with bypass logic between execution slices that reduces execution latencies between dependent instructions.

Claims14

Dependent claims

1-7. (canceled)

Dependencies are inferred from the claim text.

Facts

Application: 16/437,328Filed 11 Jun 2019
Priority: 3 Jun 2016
Published: 26 Sep 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 13/36
Handling requests for interconnection or transfer: for access to common bus or bus system
G06F 9/3828
Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage: with global bypass, e.g. between…
G06F 9/3836
Concurrent instruction execution, e.g. pipeline or look ahead: instruction issuing, e.g. dynamic instruction scheduling or out of order…
G06F 9/3838
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: dependency mechanisms, e.g. register scoreboarding

Family

Application15/172,635Continuation · filed 3 Jun 2016
Application16/437,328Continuation
US 10,417,152 B2Related patent
US 2017/0351523 A1Published application
US 2019/0294571 A1This patent

From the US filing history. Foreign family members aren’t listed.