Data output control apparatus, information processing apparatus, and data output control method

An information processing apparatus comprising:

• a processor configured to output first data or second data;
• a memory configured to store at least any of the first data and the second data;
• and
• a data output control apparatus configured to control timing at which the first data or the second data received from the processor is outputted to the memory,
• wherein the data output control apparatus includes
• an encryption executing circuit configured to receive first data from a processor with a control signal indicating whether the first data is to be encrypted, and encrypt the first data when the control signal indicates that the first data is to be encrypted,
• a selection circuit configured to output any of the encrypted first data and second data, the second data being received from the processor with the control signal indicating that the second data is not to be encrypted, and
• an output control unit configured to
• set a frequency of second timing to be smaller than a frequency of first timing, the first timing being timing at which the encrypted first data is enabled to be outputted, and the second timing being timing at which non-encrypted second data is enabled to be outputted, and
• transmit a signal to the selection circuit instructing that the second data be outputted at the second timing, in a case where the second data is received from the processor.

A method for data output control, the method comprising:

• receiving first data from a processor with a control signal indicating whether the first data is to be encrypted;
• encrypting the first data when the control signal indicates that the first data is to be encrypted;
• outputting any of the encrypted first data and second data, the second data being received from the processor with the control signal indicating that the second data is not to be encrypted;
• setting a frequency of second timing to be smaller than a frequency of first timing, the first timing being timing at which the encrypted first data is enabled to be outputted, and the second timing being timing at which non-encrypted second data is enabled to be outputted;
• and
• transmitting a signal to the selection circuit instructing that the second data be outputted at the second timing, in a case where the second data is received from the processor.