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US 2019/0294547 A1Published application
Hybrid memory system
AssigneeMicron Technology, Inc.
InventorsDanilo Caraccio, Emanuele Confalonieri, Marco Dallabora, Roberto Izzi, Paolo Amato, Daniele Balluchi, Luca Porzio
Life of this patent
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Abstract
An example apparatus comprises a hybrid memory system and a controller coupled to the hybrid memory system. The controller may be configured to cause data to be selectively stored in the hybrid memory system responsive to a determination that an exception involving the data has occurred.
Claims24
An apparatus, comprising:
- a hybrid memory system comprising a first non-volatile memory (NVM) resource and second NVM resource;
- a controller to determine that the first NVM resource or the second NVM resource exhibits a lower write latency than the other of the first NVM resource or the second NVM resource;
- and
- the controller coupled to the hybrid memory system, wherein the controller is configured to:
- determine that an exception corresponding to a read or write access request for a particular set of data is going to occur;
- and
- cause the particular set of data to be selectively stored in the first NVM or the second NVM of the hybrid memory system by mapping a logical block address (LBA) associated with a main memory coupled to the hybrid memory to the one of the first NVM or the second NVM that exhibits the lower write latency based, at least in part on a determination that the exception involving the particular set of data will occur.
4 more elements
(canceled)
An apparatus, comprising:
- a hybrid memory system comprising a first non-volatile memory (NVM) resource and second NVM resource;
- the hybrid memory system to couple to a host;
- and
- a controller to determine that the first NVM or the second NVM exhibits a lower write latency than the other of the first NVM or the second NVM;
- the controller coupled to the hybrid memory system, wherein the controller is configured to:
- cause a portion of the hybrid memory system to be allocated for use in a code paging operation;
- cause a portion of a memory associated with the host to be mapped to a logical block addressing (LBA) range;
- cause the LBA range to be mapped to the allocated portion of the hybrid memory system;
- determine that an exception corresponding to a read or write access request for a particular set of data is going to occur;
- and
- cause the particular set of data to be selectively stored in the first NVM or the second NVM of the hybrid memory system by mapping a LBA associated with a main memory coupled to the hybrid memory to the one of the first NVM or the second NVM that exhibits the lower write latency based, at least in part on performance of the code paging operation and a determination that the exception involving the particular set of data will occur.
8 more elements
A method, comprising:
- allocating a portion of a hybrid memory system comprising a flash memory device and a resistance variable memory device for use in a code paging operation;
- determining that a fault exception corresponding to a read or write access request for a particular set of data is going to occur;
- performing the code paging operation in response to determining that a host will experience a fault exception;
- and
- selectively transferring the particular set of data from the host to the allocated portion of the flash memory device or the phase change random access memory device of the hybrid memory system by mapping a logical block address (LBA) associated with a main memory coupled to the hybrid memory to the flash memory device or the resistance variable memory device that exhibits the lower write latency based, at least in part, on performance of the code paging operation and a determination that the fault exception involving the particular set of data will occur.
2 more elements
Dependencies are inferred from the claim text.