Fault tolerant memory systems and components with interconnected and redundant data interfaces
AssigneeRambus Inc.
InventorsKenneth L. Wright, Frederick A. Ware
Life of this patent
Estimating the term…
Abstract
A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.
Claims20
(canceled)
A memory controller supporting a fault mode to route data signals around potentially defective data paths, including a first potentially defective data path and a second potentially defective data path, the memory controller comprising:
- a first data link to couple to a first memory via the first potentially defective data path, the first data link to transmit first write data signals to the first memory over the first potentially defective data path in a first mode;
- and
- a second data link to couple to a second memory via the second potentially defective data path, the second data link to transmit second write data signals to the second memory over the second potentially defective data path in the first mode;
- the memory controller routing third write data signals to the second memory over the first potentially defective data path through the first memory in the fault mode.
A method for communicating with a first memory and a second memory over either or both of a potentially defective first data path and a potentially defective second data path, the method comprising:
- simultaneously transmitting first write data to the first memory via the first data path and second write data to the second memory via the second data path;
- detecting a defect in the second data path;
- entering a fault mode, responsive to the detecting, the method disabling write communication via the second data path in the fault mode;
- and
- in the fault mode, transmitting third write data to the first memory and fourth write data to the second memory via the first data path.
Dependencies are inferred from the claim text.