US 2019/0294500 A1 · MEMORY SYSTEM

Abstract

According to one embodiment, a memory system includes an error mitigation encoder that executes error mitigation coding on write data to be stored in a processing target page of a non-volatile memory, a memory interface that writes the write data which has undergone the error mitigation coding in the processing target page of the non-volatile memory and reads the write data which has undergone the error mitigation coding from the processing target page as read data, an error mitigation decoder that performs error mitigation decoding on the read data read from the processing target page of the non-volatile memory, and an error mitigation coding rate deciding unit that decides an error mitigation coding rate of the error mitigation encoder and the error mitigation decoder on the basis of at least one of information indicating the processing target page and information indicating a device characteristic of the processing target page.

Claims20

Dependent claims

A memory system, comprising:

a non-volatile memory having a plurality of memory cells each capable of storing a multi-value bit;
an error mitigation encoder that executes error mitigation coding on write data to be stored in a processing target page of the non-volatile memory;
a memory interface that writes the write data which has undergone the error mitigation coding in the processing target page of the non-volatile memory and reads the write data which has undergone the error mitigation coding from the processing target page as read data;
an error mitigation decoder that performs error mitigation decoding on the read data read from the processing target page of the non-volatile memory;
and
an error mitigation coding rate deciding unit that decides an error mitigation coding rate of the error mitigation encoder and the error mitigation decoder on the basis of at least one of information indicating the processing target page and information indicating a device characteristic of the processing target page.

3 more elements

A memory system, comprising:

a non-volatile memory;
a first error correction encoder that executes first error correction coding of adding a first parity for first error correction in an intra-page direction on write data;
an error mitigation encoder that executes error mitigation coding on the write data which has undergone the first error correction coding;
a second error correction encoder that executes second error correction coding of adding a second parity for second error correction in an inter-page direction on the write data which has undergone the error mitigation coding;
a memory interface that writes the write data which has undergone the second error correction coding in the non-volatile memory and reads the write data which has undergone the second error correction coding from the non-volatile memory as read data;
a second error correction decoder that performs the second error correction on the read data read from the non-volatile memory;
an error mitigation decoder that executes error mitigation decoding on the read data which has undergone the second error correction;
and
a first error correction decoder that performs first error correction on the read data which has undergone the error mitigation decoding.

6 more elements

Dependencies are inferred from the claim text.

Memory system

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Memory system

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Abstract

Claims20