US 2019/0294443 A1 · PROVIDING EARLY PIPELINE OPTIMIZATION OF CONDITIONAL INSTRUCTIONS IN PROCESSOR-BASED SYSTEMS

Abstract

Providing early pipeline optimization of conditional instructions in processor-based systems is disclosed. In one aspect, an instruction pipeline of a processor-based system detects a mispredicted branch (i.e., following a misprediction of a condition associated with a speculatively executed conditional branch instruction), and records a current state of one or more condition flags as a condition flags snapshot. After a pipeline flush is initiated and a corrected fetch path is restarted, an instruction decode stage of the instruction pipeline uses the condition flags snapshot to apply optimizations to conditional instructions detected within the corrected fetch path. According to some aspects, the condition flags snapshot is subsequently invalidated upon encountering a condition-flag-writing instruction within the corrected fetch path. In this manner, the condition flags snapshot enables non-speculative (with respect to the corrected fetch path) resolution of conditional instructions earlier within the instruction pipeline, thus conserving system resources and improving processor performance.

Claims21

Dependent claims

A processor-based system for providing early pipeline optimization of conditional instructions, comprising an instruction pipeline comprising an instruction fetch stage, an instruction decode stage, an execution stage, and a register writeback stage;

the execution stage of the instruction pipeline configured to:
detect a mispredicted branch within an original fetch path;
and
responsive to the mispredicted branch, initiate a pipeline flush to begin a corrected fetch path;
the register writeback stage of the instruction pipeline configured to, responsive to the mispredicted branch, provide a condition flags snapshot comprising a current state of one or more condition flags to the instruction fetch stage of the instruction pipeline;
and
the instruction decode stage of the instruction pipeline configured to:
detect a conditional instruction within the corrected fetch path;
and
apply an optimization to the conditional instruction based on the condition flags snapshot.

7 more elements

A method for providing early pipeline optimization of conditional instructions, comprising:

detecting, by an execution stage of an instruction pipeline, a mispredicted branch within an original fetch path;
responsive to the mispredicted branch:
initiating, by the execution stage, a pipeline flush to begin a corrected fetch path;
and
providing, by a register writeback stage of the instruction pipeline, a condition flags snapshot comprising a current state of one or more condition flags to an instruction fetch stage of the instruction pipeline;
detecting, by an instruction decode stage of the instruction pipeline, a conditional instruction within the corrected fetch path;
and
applying, by the instruction decode stage, an optimization to the conditional instruction based on the condition flags snapshot.

5 more elements

A non-transitory computer-readable medium having stored thereon computer-readable instructions to cause a processor to:

detect a mispredicted branch within an original fetch path of an instruction pipeline of the processor;
responsive to the mispredicted branch:
initiate a pipeline flush to begin a corrected fetch path;
and
provide a condition flags snapshot comprising a current state of one or more condition flags to an instruction fetch stage of the instruction pipeline;
detect a conditional instruction within the corrected fetch path;
and
apply an optimization to the conditional instruction based on the condition flags snapshot.

5 more elements

Dependencies are inferred from the claim text.

Providing early pipeline optimization of conditional instructions in processor-based systems

Life of this patent

Providing early pipeline optimization of conditional instructions in processor-based systems

Life of this patent

Abstract

Claims21